Lines Matching refs:addr
46 #define MMI_LWX(reg, addr, stride, bias) \
48 PTR_ADDU "$at, "#addr", "#stride" \n\t" \
52 #define MMI_SWX(reg, addr, stride, bias) \
54 PTR_ADDU "$at, "#addr", "#stride" \n\t" \
58 #define MMI_LDX(reg, addr, stride, bias) \
60 PTR_ADDU "$at, "#addr", "#stride" \n\t" \
64 #define MMI_SDX(reg, addr, stride, bias) \
66 PTR_ADDU "$at, "#addr", "#stride" \n\t" \
70 #define MMI_LWC1(fp, addr, bias) \
71 "lwc1 "#fp", "#bias"("#addr") \n\t"
73 #define MMI_ULWC1(fp, addr, bias) \
75 "ulw $at, "#bias"("#addr") \n\t" \
79 #define MMI_LWXC1(fp, addr, stride, bias) \
81 PTR_ADDU "$at, "#addr", "#stride" \n\t" \
85 #define MMI_SWC1(fp, addr, bias) \
86 "swc1 "#fp", "#bias"("#addr") \n\t"
88 #define MMI_USWC1(fp, addr, bias) \
91 "usw $at, "#bias"("#addr") \n\t" \
94 #define MMI_SWXC1(fp, addr, stride, bias) \
96 PTR_ADDU "$at, "#addr", "#stride" \n\t" \
100 #define MMI_LDC1(fp, addr, bias) \
101 "ldc1 "#fp", "#bias"("#addr") \n\t"
103 #define MMI_ULDC1(fp, addr, bias) \
105 "uld $at, "#bias"("#addr") \n\t" \
109 #define MMI_LDXC1(fp, addr, stride, bias) \
111 PTR_ADDU "$at, "#addr", "#stride" \n\t" \
115 #define MMI_SDC1(fp, addr, bias) \
116 "sdc1 "#fp", "#bias"("#addr") \n\t"
118 #define MMI_USDC1(fp, addr, bias) \
121 "usd $at, "#bias"("#addr") \n\t" \
124 #define MMI_SDXC1(fp, addr, stride, bias) \
126 PTR_ADDU "$at, "#addr", "#stride" \n\t" \
130 #define MMI_LQ(reg1, reg2, addr, bias) \
131 "ld "#reg1", "#bias"("#addr") \n\t" \
132 "ld "#reg2", 8+"#bias"("#addr") \n\t"
134 #define MMI_SQ(reg1, reg2, addr, bias) \
135 "sd "#reg1", "#bias"("#addr") \n\t" \
136 "sd "#reg2", 8+"#bias"("#addr") \n\t"
138 #define MMI_LQC1(fp1, fp2, addr, bias) \
139 "ldc1 "#fp1", "#bias"("#addr") \n\t" \
140 "ldc1 "#fp2", 8+"#bias"("#addr") \n\t"
142 #define MMI_SQC1(fp1, fp2, addr, bias) \
143 "sdc1 "#fp1", "#bias"("#addr") \n\t" \
144 "sdc1 "#fp2", 8+"#bias"("#addr") \n\t"
148 #define MMI_LWX(reg, addr, stride, bias) \
149 "gslwx "#reg", "#bias"("#addr", "#stride") \n\t"
151 #define MMI_SWX(reg, addr, stride, bias) \
152 "gsswx "#reg", "#bias"("#addr", "#stride") \n\t"
154 #define MMI_LDX(reg, addr, stride, bias) \
155 "gsldx "#reg", "#bias"("#addr", "#stride") \n\t"
157 #define MMI_SDX(reg, addr, stride, bias) \
158 "gssdx "#reg", "#bias"("#addr", "#stride") \n\t"
160 #define MMI_LWC1(fp, addr, bias) \
161 "lwc1 "#fp", "#bias"("#addr") \n\t"
165 #define MMI_LWLRC1(fp, addr, bias, off) \
167 "lwl $at, "#bias"+"#off"("#addr") \n\t" \
168 "lwr $at, "#bias"("#addr") \n\t" \
177 #define MMI_ULWC1(fp, addr, bias) \
178 "gslwlc1 "#fp", 3+"#bias"("#addr") \n\t" \
179 "gslwrc1 "#fp", "#bias"("#addr") \n\t"
183 #define MMI_LWXC1(fp, addr, stride, bias) \
184 "gslwxc1 "#fp", "#bias"("#addr", "#stride") \n\t"
186 #define MMI_SWC1(fp, addr, bias) \
187 "swc1 "#fp", "#bias"("#addr") \n\t"
189 #define MMI_USWC1(fp, addr, bias) \
190 "gsswlc1 "#fp", 3+"#bias"("#addr") \n\t" \
191 "gsswrc1 "#fp", "#bias"("#addr") \n\t"
193 #define MMI_SWXC1(fp, addr, stride, bias) \
194 "gsswxc1 "#fp", "#bias"("#addr", "#stride") \n\t"
196 #define MMI_LDC1(fp, addr, bias) \
197 "ldc1 "#fp", "#bias"("#addr") \n\t"
199 #define MMI_ULDC1(fp, addr, bias) \
200 "gsldlc1 "#fp", 7+"#bias"("#addr") \n\t" \
201 "gsldrc1 "#fp", "#bias"("#addr") \n\t"
203 #define MMI_LDXC1(fp, addr, stride, bias) \
204 "gsldxc1 "#fp", "#bias"("#addr", "#stride") \n\t"
206 #define MMI_SDC1(fp, addr, bias) \
207 "sdc1 "#fp", "#bias"("#addr") \n\t"
209 #define MMI_USDC1(fp, addr, bias) \
210 "gssdlc1 "#fp", 7+"#bias"("#addr") \n\t" \
211 "gssdrc1 "#fp", "#bias"("#addr") \n\t"
213 #define MMI_SDXC1(fp, addr, stride, bias) \
214 "gssdxc1 "#fp", "#bias"("#addr", "#stride") \n\t"
216 #define MMI_LQ(reg1, reg2, addr, bias) \
217 "gslq "#reg1", "#reg2", "#bias"("#addr") \n\t"
219 #define MMI_SQ(reg1, reg2, addr, bias) \
220 "gssq "#reg1", "#reg2", "#bias"("#addr") \n\t"
222 #define MMI_LQC1(fp1, fp2, addr, bias) \
223 "gslqc1 "#fp1", "#fp2", "#bias"("#addr") \n\t"
225 #define MMI_SQC1(fp1, fp2, addr, bias) \
226 "gssqc1 "#fp1", "#fp2", "#bias"("#addr") \n\t"