Lines Matching refs:v4i32
37 #define LD_SW(...) LD_V(v4i32, __VA_ARGS__)
45 #define ST_SW(...) ST_V(v4i32, __VA_ARGS__)
281 #define LD_SW2(...) LD_V2(v4i32, __VA_ARGS__)
300 #define LD_SW4(...) LD_V4(v4i32, __VA_ARGS__)
339 #define LD_SW8(...) LD_V8(v4i32, __VA_ARGS__)
367 #define ST_SW2(...) ST_V2(v4i32, __VA_ARGS__)
377 #define ST_SW4(...) ST_V4(v4i32, __VA_ARGS__)
393 #define ST_SW8(...) ST_V8(v4i32, __VA_ARGS__)
447 out0_m = __msa_copy_u_w((v4i32) in, idx); \
453 out0_m = __msa_copy_u_w((v4i32) in, idx0); \
454 out1_m = __msa_copy_u_w((v4i32) in, idx1); \
461 out0_m = __msa_copy_u_w((v4i32) in, idx0); \
462 out1_m = __msa_copy_u_w((v4i32) in, idx1); \
463 out2_m = __msa_copy_u_w((v4i32) in, idx2); \
464 out3_m = __msa_copy_u_w((v4i32) in, idx3); \
544 out8_m = __msa_copy_u_w((v4i32) in0, 2); \
545 out9_m = __msa_copy_u_w((v4i32) in1, 2); \
546 out10_m = __msa_copy_u_w((v4i32) in2, 2); \
547 out11_m = __msa_copy_u_w((v4i32) in3, 2); \
548 out12_m = __msa_copy_u_w((v4i32) in4, 2); \
549 out13_m = __msa_copy_u_w((v4i32) in5, 2); \
550 out14_m = __msa_copy_u_w((v4i32) in6, 2); \
551 out15_m = __msa_copy_u_w((v4i32) in7, 2); \
625 #define SLDI_B2_SW(...) SLDI_B2(v4i32, __VA_ARGS__)
718 out0 = (RTYPE) __msa_vshf_w((v4i32) mask0, (v4i32) in1, (v4i32) in0); \
719 out1 = (RTYPE) __msa_vshf_w((v4i32) mask1, (v4i32) in3, (v4i32) in2); \
803 #define DOTP_SH2_SW(...) DOTP_SH2(v4i32, __VA_ARGS__)
812 #define DOTP_SH4_SW(...) DOTP_SH4(v4i32, __VA_ARGS__)
878 out0 = (RTYPE) __msa_dpadd_s_w((v4i32) out0, \
880 out1 = (RTYPE) __msa_dpadd_s_w((v4i32) out1, \
883 #define DPADD_SH2_SW(...) DPADD_SH2(v4i32, __VA_ARGS__)
891 #define DPADD_SH4_SW(...) DPADD_SH4(v4i32, __VA_ARGS__)
968 in = __msa_maxi_s_w((v4i32) in, 0); \
969 in = (v4i32) __msa_sat_u_w((v4u32) in, 7); \
1003 res0_m = __msa_hadd_s_d((v4i32) in, (v4i32) in); \
1006 sum_m = __msa_copy_s_w((v4i32) res0_m, 0); \
1027 sum_m = __msa_copy_u_w((v4i32) res0_m, 0); \
1140 out = (RTYPE) __msa_insert_w((v4i32) out, 0, in0); \
1141 out = (RTYPE) __msa_insert_w((v4i32) out, 1, in1); \
1148 out = (RTYPE) __msa_insert_w((v4i32) out, 0, in0); \
1149 out = (RTYPE) __msa_insert_w((v4i32) out, 1, in1); \
1150 out = (RTYPE) __msa_insert_w((v4i32) out, 2, in2); \
1151 out = (RTYPE) __msa_insert_w((v4i32) out, 3, in3); \
1156 #define INSERT_W4_SW(...) INSERT_W4(v4i32, __VA_ARGS__)
1209 #define ILVEV_H2_SW(...) ILVEV_H2(v4i32, __VA_ARGS__)
1222 out0 = (RTYPE) __msa_ilvev_w((v4i32) in1, (v4i32) in0); \
1223 out1 = (RTYPE) __msa_ilvev_w((v4i32) in3, (v4i32) in2); \
1246 #define ILVEV_D2_SW(...) ILVEV_D2(v4i32, __VA_ARGS__)
1293 #define ILVL_H2_SW(...) ILVL_H2(v4i32, __VA_ARGS__)
1302 #define ILVL_H4_SW(...) ILVL_H4(v4i32, __VA_ARGS__)
1315 out0 = (RTYPE) __msa_ilvl_w((v4i32) in0, (v4i32) in1); \
1316 out1 = (RTYPE) __msa_ilvl_w((v4i32) in2, (v4i32) in3); \
1341 #define ILVR_B2_SW(...) ILVR_B2(v4i32, __VA_ARGS__)
1363 #define ILVR_B4_SW(...) ILVR_B4(v4i32, __VA_ARGS__)
1375 #define ILVR_B8_SW(...) ILVR_B8(v4i32, __VA_ARGS__)
1393 #define ILVR_H2_SW(...) ILVR_H2(v4i32, __VA_ARGS__)
1409 #define ILVR_H4_SW(...) ILVR_H4(v4i32, __VA_ARGS__)
1413 out0 = (RTYPE) __msa_ilvr_w((v4i32) in0, (v4i32) in1); \
1414 out1 = (RTYPE) __msa_ilvr_w((v4i32) in2, (v4i32) in3); \
1499 #define ILVRL_B2_SW(...) ILVRL_B2(v4i32, __VA_ARGS__)
1509 #define ILVRL_H2_SW(...) ILVRL_H2(v4i32, __VA_ARGS__)
1513 out0 = (RTYPE) __msa_ilvr_w((v4i32) in0, (v4i32) in1); \
1514 out1 = (RTYPE) __msa_ilvl_w((v4i32) in0, (v4i32) in1); \
1518 #define ILVRL_W2_SW(...) ILVRL_W2(v4i32, __VA_ARGS__)
1629 in0 = (RTYPE) __msa_sat_s_w((v4i32) in0, sat_val); \
1630 in1 = (RTYPE) __msa_sat_s_w((v4i32) in1, sat_val); \
1632 #define SAT_SW2_SW(...) SAT_SW2(v4i32, __VA_ARGS__)
1639 #define SAT_SW4_SW(...) SAT_SW4(v4i32, __VA_ARGS__)
1689 out0 = (RTYPE) __msa_splati_w((v4i32) in, stidx); \
1690 out1 = (RTYPE) __msa_splati_w((v4i32) in, (stidx+1)); \
1693 #define SPLATI_W2_SW(...) SPLATI_W2(v4i32, __VA_ARGS__)
1701 #define SPLATI_W4_SW(...) SPLATI_W4(v4i32, __VA_ARGS__)
1722 #define PCKEV_B2_SW(...) PCKEV_B2(v4i32, __VA_ARGS__)
1741 #define PCKEV_B4_SW(...) PCKEV_B4(v4i32, __VA_ARGS__)
1760 #define PCKEV_H2_SW(...) PCKEV_H2(v4i32, __VA_ARGS__)
1769 #define PCKEV_H4_SW(...) PCKEV_H4(v4i32, __VA_ARGS__)
2031 in0 = (RTYPE) __msa_srar_w((v4i32) in0, (v4i32) shift); \
2032 in1 = (RTYPE) __msa_srar_w((v4i32) in1, (v4i32) shift); \
2034 #define SRAR_W2_SW(...) SRAR_W2(v4i32, __VA_ARGS__)
2041 #define SRAR_W4_SW(...) SRAR_W4(v4i32, __VA_ARGS__)
2081 in0 = (RTYPE) __msa_srari_w((v4i32) in0, shift); \
2082 in1 = (RTYPE) __msa_srari_w((v4i32) in1, shift); \
2084 #define SRARI_W2_SW(...) SRARI_W2(v4i32, __VA_ARGS__)
2092 #define SRARI_W4_SW(...) SRARI_W4(v4i32, __VA_ARGS__)
2177 out = (v4i32) __msa_ilvr_h(sign_m, (v8i16) in); \
2442 out0 = (v16u8) __msa_ilvev_w((v4i32) tmp3_m, (v4i32) tmp2_m); \
2443 out4 = (v16u8) __msa_ilvod_w((v4i32) tmp3_m, (v4i32) tmp2_m); \
2447 out2 = (v16u8) __msa_ilvev_w((v4i32) tmp3_m, (v4i32) tmp2_m); \
2448 out6 = (v16u8) __msa_ilvod_w((v4i32) tmp3_m, (v4i32) tmp2_m); \
2451 out1 = (v16u8) __msa_ilvev_w((v4i32) tmp3_m, (v4i32) tmp2_m); \
2452 out5 = (v16u8) __msa_ilvod_w((v4i32) tmp3_m, (v4i32) tmp2_m); \
2456 out3 = (v16u8) __msa_ilvev_w((v4i32) tmp3_m, (v4i32) tmp2_m); \
2457 out7 = (v16u8) __msa_ilvod_w((v4i32) tmp3_m, (v4i32) tmp2_m); \
2515 v4i32 s0_m, s1_m, s2_m, s3_m; \
2520 out0 = (v4i32) __msa_ilvr_d((v2i64) s2_m, (v2i64) s0_m); \
2521 out1 = (v4i32) __msa_ilvl_d((v2i64) s2_m, (v2i64) s0_m); \
2522 out2 = (v4i32) __msa_ilvr_d((v2i64) s3_m, (v2i64) s1_m); \
2523 out3 = (v4i32) __msa_ilvl_d((v2i64) s3_m, (v2i64) s1_m); \
2714 out0_m = __msa_copy_u_w((v4i32) dst0_m, 0); \
2715 out1_m = __msa_copy_u_w((v4i32) dst0_m, 1); \
2716 out2_m = __msa_copy_u_w((v4i32) dst1_m, 0); \
2717 out3_m = __msa_copy_u_w((v4i32) dst1_m, 1); \
2787 out0_m = __msa_copy_u_w((v4i32) tmp0_m, 0); \
2788 out1_m = __msa_copy_u_w((v4i32) tmp0_m, 2); \
2789 out2_m = __msa_copy_u_w((v4i32) tmp1_m, 0); \
2790 out3_m = __msa_copy_u_w((v4i32) tmp1_m, 2); \