Lines Matching refs:src1
37 #define MMI_PCMPGTUB(dst, src1, src2) \
38 "pcmpeqb %[db_1], "#src1", "#src2" \n\t" \
39 "pmaxub %[db_2], "#src1", "#src2" \n\t" \
40 "pcmpeqb %[db_2], %[db_2], "#src1" \n\t" \
258 #define PUT_VP8_EPEL4_V6_MMI(src, src1, dst, srcstride) \
263 PTR_SUBU ""#src1", "#src", "#srcstride" \n\t" \
264 MMI_ULWC1(%[ftmp1], src1, 0x00) \
269 PTR_SUBU ""#src1", "#src1", "#srcstride" \n\t" \
270 MMI_ULWC1(%[ftmp1], src1, 0x00) \
275 PTR_ADDU ""#src1", "#src", "#srcstride" \n\t" \
276 MMI_ULWC1(%[ftmp1], src1, 0x00) \
280 PTR_ADDU ""#src1", "#src1", "#srcstride" \n\t" \
281 MMI_ULWC1(%[ftmp1], src1, 0x00) \
286 PTR_ADDU ""#src1", "#src1", "#srcstride" \n\t" \
287 MMI_ULWC1(%[ftmp1], src1, 0x00) \
301 #define PUT_VP8_EPEL4_V4_MMI(src, src1, dst, srcstride) \
306 PTR_SUBU ""#src1", "#src", "#srcstride" \n\t" \
307 MMI_ULWC1(%[ftmp1], src1, 0x00) \
312 PTR_ADDU ""#src1", "#src", "#srcstride" \n\t" \
313 MMI_ULWC1(%[ftmp1], src1, 0x00) \
317 PTR_ADDU ""#src1", "#src1", "#srcstride" \n\t" \
318 MMI_ULWC1(%[ftmp1], src1, 0x00) \
430 #define PUT_VP8_EPEL8_V6_MMI(src, src1, dst, srcstride) \
437 PTR_SUBU ""#src1", "#src", "#srcstride" \n\t" \
438 MMI_ULDC1(%[ftmp1], src1, 0x00) \
446 PTR_SUBU ""#src1", "#src1", "#srcstride" \n\t" \
447 MMI_ULDC1(%[ftmp1], src1, 0x00) \
455 PTR_ADDU ""#src1", "#src", "#srcstride" \n\t" \
456 MMI_ULDC1(%[ftmp1], src1, 0x00) \
462 PTR_ADDU ""#src1", "#src1", "#srcstride" \n\t" \
463 MMI_ULDC1(%[ftmp1], src1, 0x00) \
471 PTR_ADDU ""#src1", "#src1", "#srcstride" \n\t" \
472 MMI_ULDC1(%[ftmp1], src1, 0x00) \
492 #define PUT_VP8_EPEL8_V4_MMI(src, src1, dst, srcstride) \
499 PTR_SUBU ""#src1", "#src", "#srcstride" \n\t" \
500 MMI_ULDC1(%[ftmp1], src1, 0x00) \
508 PTR_ADDU ""#src1", "#src", "#srcstride" \n\t" \
509 MMI_ULDC1(%[ftmp1], src1, 0x00) \
515 PTR_ADDU ""#src1", "#src1", "#srcstride" \n\t" \
516 MMI_ULDC1(%[ftmp1], src1, 0x00) \
577 #define PUT_VP8_BILINEAR8_V_MMI(src, src1, dst, sstride) \
584 PTR_ADDU ""#src1", "#src", "#sstride" \n\t" \
585 MMI_ULDC1(%[ftmp1], src1, 0x00) \
602 #define PUT_VP8_BILINEAR4_V_MMI(src, src1, dst, sstride) \
607 PTR_ADDU ""#src1", "#src", "#sstride" \n\t" \
608 MMI_ULWC1(%[ftmp1], src1, 0x00) \
1580 mips_reg src1, dst1;
1614 PTR_ADDIU "%[src1], %[src], 0x08 \n\t"
1617 PUT_VP8_EPEL8_H4_MMI(%[src1], %[dst1])
1630 [dst1]"=&r"(dst1), [src1]"=&r"(src1),
1794 mips_reg src1, dst1;
1836 PTR_ADDIU "%[src1], %[src], 0x08 \n\t"
1839 PUT_VP8_EPEL8_H6_MMI(%[src1], %[dst1])
1852 [dst1]"=&r"(dst1), [src1]"=&r"(src1),
2026 mips_reg src0, src1, dst0;
2063 PUT_VP8_EPEL8_V4_MMI(%[src], %[src1], %[dst], %[srcstride])
2067 PUT_VP8_EPEL8_V4_MMI(%[src0], %[src1], %[dst], %[srcstride])
2081 [src1]"=&r"(src1),
2112 mips_reg src1;
2139 PUT_VP8_EPEL8_V4_MMI(%[src], %[src1], %[dst], %[srcstride])
2152 [src1]"=&r"(src1),
2183 mips_reg src1;
2206 PUT_VP8_EPEL4_V4_MMI(%[src], %[src1], %[dst], %[srcstride])
2217 [src1]"=&r"(src1),
2248 mips_reg src0, src1, dst0;
2289 PUT_VP8_EPEL8_V6_MMI(%[src], %[src1], %[dst], %[srcstride])
2293 PUT_VP8_EPEL8_V6_MMI(%[src0], %[src1], %[dst0], %[srcstride])
2307 [src1]"=&r"(src1),
2339 mips_reg src1;
2370 PUT_VP8_EPEL8_V6_MMI(%[src], %[src1], %[dst], %[srcstride])
2383 [src1]"=&r"(src1),
2415 mips_reg src1;
2442 PUT_VP8_EPEL4_V6_MMI(%[src], %[src1], %[dst], %[srcstride])
2453 [src1]"=&r"(src1),
3030 mips_reg src0, src1, dst0;
3054 PUT_VP8_BILINEAR8_V_MMI(%[src], %[src1], %[dst], %[sstride])
3058 PUT_VP8_BILINEAR8_V_MMI(%[src0], %[src1], %[dst0], %[sstride])
3071 [src1]"=&r"(src1),
3196 mips_reg src1;
3219 PUT_VP8_BILINEAR8_V_MMI(%[src], %[src1], %[dst], %[sstride])
3231 [src1]"=&r"(src1),
3353 mips_reg src1;
3373 PUT_VP8_BILINEAR4_V_MMI(%[src], %[src1], %[dst], %[sstride])
3385 [src1]"=&r"(src1),