Lines Matching refs:addr1
160 PTR_ADDU "%[addr1], %[block], %[line_size] \n\t"
162 MMI_ULWC1(%[ftmp3], %[addr1], 0x00)
169 MMI_SWC1(%[ftmp1], %[addr1], 0x00)
171 PTR_ADDU "%[block], %[addr1], %[line_size] \n\t"
177 [addr0]"=&r"(addr[0]), [addr1]"=&r"(addr[1]),
199 PTR_ADDU "%[addr1], %[block], %[line_size] \n\t"
201 MMI_ULDC1(%[ftmp3], %[addr1], 0x00)
212 PTR_ADDU "%[addr1], %[block], %[line_size] \n\t"
214 MMI_ULDC1(%[ftmp3], %[addr1], 0x00)
228 [addr0]"=&r"(addr[0]), [addr1]"=&r"(addr[1]),
317 PTR_ADDU "%[addr1], %[src2], %[src_stride2] \n\t"
319 MMI_ULWC1(%[ftmp3], %[addr1], 0x00)
321 PTR_ADDU "%[src2], %[addr1], %[src_stride2] \n\t"
337 [addr0]"=&r"(addr[0]), [addr1]"=&r"(addr[1]),
366 PTR_ADDU "%[addr1], %[src2], %[src_stride2] \n\t"
367 MMI_ULDC1(%[ftmp3], %[addr1], 0x00)
380 PTR_ADDU "%[addr1], %[src2], %[src_stride2] \n\t"
381 MMI_ULDC1(%[ftmp3], %[addr1], 0x00)
396 [addr0]"=&r"(addr[0]), [addr1]"=&r"(addr[1]),
429 PTR_ADDU "%[addr1], %[src2], %[src_stride2] \n\t"
431 MMI_ULDC1(%[ftmp3], %[addr1], 0x00)
433 MMI_ULDC1(%[ftmp7], %[addr1], 0x08)
451 PTR_ADDU "%[addr1], %[src2], %[src_stride2] \n\t"
453 MMI_ULDC1(%[ftmp3], %[addr1], 0x00)
455 MMI_ULDC1(%[ftmp7], %[addr1], 0x08)
475 [addr0]"=&r"(addr[0]), [addr1]"=&r"(addr[1]),
500 PTR_ADDU "%[addr1], %[src2], %[src_stride2] \n\t"
502 MMI_ULWC1(%[ftmp3], %[addr1], 0x00)
504 PTR_ADDU "%[src2], %[addr1], %[src_stride2] \n\t"
522 [addr0]"=&r"(addr[0]), [addr1]"=&r"(addr[1]),
551 PTR_ADDU "%[addr1], %[src2], %[src_stride2] \n\t"
553 MMI_ULDC1(%[ftmp3], %[addr1], 0x00)
570 PTR_ADDU "%[addr1], %[src2], %[src_stride2] \n\t"
572 MMI_ULDC1(%[ftmp3], %[addr1], 0x00)
593 [addr0]"=&r"(addr[0]), [addr1]"=&r"(addr[1]),
677 PTR_ADDU "%[addr1], %[src2], %[src_stride2] \n\t"
678 MMI_ULDC1(%[ftmp3], %[addr1], 0x00)
697 PTR_ADDU "%[addr1], %[src2], %[src_stride2] \n\t"
698 MMI_ULDC1(%[ftmp3], %[addr1], 0x00)
720 [addr0]"=&r"(addr[0]), [addr1]"=&r"(addr[1]),
876 PTR_ADDU "%[addr1], %[pixels], %[addr0] \n\t"
877 MMI_ULDC1(%[ftmp0], %[addr1], 0x00)
878 MMI_ULDC1(%[ftmp2], %[addr1], 0x01)
896 PTR_ADDU "%[addr1], %[pixels], %[addr0] \n\t"
897 MMI_ULDC1(%[ftmp2], %[addr1], 0x00)
898 MMI_ULDC1(%[ftmp4], %[addr1], 0x01)
925 [addr0]"=&r"(addr[0]), [addr1]"=&r"(addr[1]),