Lines Matching refs:addr0
157 PTR_ADDU "%[addr0], %[pixels], %[line_size] \n\t"
159 MMI_ULWC1(%[ftmp1], %[addr0], 0x00)
170 PTR_ADDU "%[pixels], %[addr0], %[line_size] \n\t"
177 [addr0]"=&r"(addr[0]), [addr1]"=&r"(addr[1]),
197 PTR_ADDU "%[addr0], %[pixels], %[line_size] \n\t"
198 MMI_ULDC1(%[ftmp1], %[addr0], 0x00)
210 PTR_ADDU "%[addr0], %[pixels], %[line_size] \n\t"
211 MMI_ULDC1(%[ftmp1], %[addr0], 0x00)
228 [addr0]"=&r"(addr[0]), [addr1]"=&r"(addr[1]),
255 PTR_ADDU "%[addr0], %[block], %[line_size] \n\t"
256 MMI_ULDC1(%[ftmp3], %[addr0], 0x00)
257 MMI_ULDC1(%[ftmp7], %[addr0], 0x08)
264 MMI_SDC1(%[ftmp1], %[addr0], 0x00)
265 MMI_SDC1(%[ftmp5], %[addr0], 0x08)
266 PTR_ADDU "%[block], %[addr0], %[line_size] \n\t"
276 PTR_ADDU "%[addr0], %[block], %[line_size] \n\t"
277 MMI_ULDC1(%[ftmp3], %[addr0], 0x00)
278 MMI_ULDC1(%[ftmp7], %[addr0], 0x08)
285 MMI_SDC1(%[ftmp1], %[addr0], 0x00)
286 MMI_SDC1(%[ftmp5], %[addr0], 0x08)
287 PTR_ADDU "%[block], %[addr0], %[line_size] \n\t"
295 [addr0]"=&r"(addr[0]),
314 PTR_ADDU "%[addr0], %[src1], %[src_stride1] \n\t"
316 MMI_ULWC1(%[ftmp1], %[addr0], 0x00)
320 PTR_ADDU "%[src1], %[addr0], %[src_stride1] \n\t"
337 [addr0]"=&r"(addr[0]), [addr1]"=&r"(addr[1]),
363 PTR_ADDU "%[addr0], %[src1], %[src_stride1] \n\t"
364 MMI_ULDC1(%[ftmp1], %[addr0], 0x00)
377 PTR_ADDU "%[addr0], %[src1], %[src_stride1] \n\t"
378 MMI_ULDC1(%[ftmp1], %[addr0], 0x00)
396 [addr0]"=&r"(addr[0]), [addr1]"=&r"(addr[1]),
424 PTR_ADDU "%[addr0], %[src1], %[src_stride1] \n\t"
426 MMI_ULDC1(%[ftmp1], %[addr0], 0x00)
427 MMI_ULDC1(%[ftmp5], %[addr0], 0x08)
446 PTR_ADDU "%[addr0], %[src1], %[src_stride1] \n\t"
448 MMI_ULDC1(%[ftmp1], %[addr0], 0x00)
449 MMI_ULDC1(%[ftmp5], %[addr0], 0x08)
475 [addr0]"=&r"(addr[0]), [addr1]"=&r"(addr[1]),
497 PTR_ADDU "%[addr0], %[src1], %[src_stride1] \n\t"
499 MMI_ULWC1(%[ftmp1], %[addr0], 0x00)
503 PTR_ADDU "%[src1], %[addr0], %[src_stride1] \n\t"
522 [addr0]"=&r"(addr[0]), [addr1]"=&r"(addr[1]),
549 PTR_ADDU "%[addr0], %[src1], %[src_stride1] \n\t"
550 MMI_ULDC1(%[ftmp1], %[addr0], 0x00)
568 PTR_ADDU "%[addr0], %[src1], %[src_stride1] \n\t"
569 MMI_ULDC1(%[ftmp1], %[addr0], 0x00)
593 [addr0]"=&r"(addr[0]), [addr1]"=&r"(addr[1]),
674 PTR_ADDU "%[addr0], %[src1], %[src_stride1] \n\t"
675 MMI_ULDC1(%[ftmp1], %[addr0], 0x00)
694 PTR_ADDU "%[addr0], %[src1], %[src_stride1] \n\t"
695 MMI_ULDC1(%[ftmp1], %[addr0], 0x00)
720 [addr0]"=&r"(addr[0]), [addr1]"=&r"(addr[1]),
851 "dli %[addr0], 0x0f \n\t"
853 "dmtc1 %[addr0], %[ftmp8] \n\t"
854 "dli %[addr0], 0x01 \n\t"
856 "dmtc1 %[addr0], %[ftmp8] \n\t"
859 "dli %[addr0], 0x02 \n\t"
860 "dmtc1 %[addr0], %[ftmp9] \n\t"
871 "xor %[addr0], %[addr0], %[addr0] \n\t"
876 PTR_ADDU "%[addr1], %[pixels], %[addr0] \n\t"
894 MMI_SDXC1(%[ftmp4], %[block], %[addr0], 0x00)
895 PTR_ADDU "%[addr0], %[addr0], %[line_size] \n\t"
896 PTR_ADDU "%[addr1], %[pixels], %[addr0] \n\t"
914 MMI_SDXC1(%[ftmp0], %[block], %[addr0], 0x00)
915 PTR_ADDU "%[addr0], %[addr0], %[line_size] \n\t"
925 [addr0]"=&r"(addr[0]), [addr1]"=&r"(addr[1]),