Lines Matching defs:reg0
435 __m128i tmp0, tmp1, tmp2, tmp3, reg0, reg1;
439 reg0 = __lsx_vreplgr2vr_h(top_left);
447 DUP4_ARG2(__lsx_vssub_hu, dst0, reg0, dst1, reg0, dst2, reg0, dst3, reg0,
467 __m128i reg0, reg1;
469 reg0 = __lsx_vreplgr2vr_h(top_left);
483 DUP4_ARG2(__lsx_vssub_hu, src0, reg0, src1, reg0, src2, reg0, src3, reg0,
485 DUP4_ARG2(__lsx_vssub_hu, src4, reg0, src5, reg0, src6, reg0, src7, reg0,
517 __m128i reg0, reg1;
522 reg0 = __lsx_vreplgr2vr_h(top_left);
536 DUP4_ARG2(__lsx_vssub_hu, src0, reg0, src1, reg0, src2, reg0, src3, reg0,
538 DUP4_ARG2(__lsx_vssub_hu, src4, reg0, src5, reg0, src6, reg0, src7, reg0,
550 DUP4_ARG2(__lsx_vssub_hu, src0, reg0, src1, reg0, src2, reg0, src3, reg0,
552 DUP4_ARG2(__lsx_vssub_hu, src4, reg0, src5, reg0, src6, reg0, src7, reg0,
564 DUP4_ARG2(__lsx_vssub_hu, src0, reg0, src1, reg0, src2, reg0, src3, reg0,
566 DUP4_ARG2(__lsx_vssub_hu, src4, reg0, src5, reg0, src6, reg0, src7, reg0,
578 DUP4_ARG2(__lsx_vssub_hu, src0, reg0, src1, reg0, src2, reg0, src3, reg0,
580 DUP4_ARG2(__lsx_vssub_hu, src4, reg0, src5, reg0, src6, reg0, src7, reg0,
600 __m128i tmp0, tmp1, tmp2, tmp3, reg0, reg1, reg2;
604 reg0 = __lsx_vreplgr2vr_h(top_left);
616 DUP4_ARG2(__lsx_vssub_hu, src0, reg0, src1, reg0, src2, reg0, src3,
617 reg0, src0, src1, src2, src3);
618 DUP4_ARG2(__lsx_vssub_hu, src4, reg0, src5, reg0, src6, reg0, src7,
619 reg0, src4, src5, src6, src7);
624 DUP4_ARG2(__lsx_vssub_hu, dst0, reg0, dst1, reg0, dst2, reg0, dst3,
625 reg0, dst0, dst1, dst2, dst3);
626 DUP4_ARG2(__lsx_vssub_hu, dst4, reg0, dst5, reg0, dst6, reg0, dst7,
627 reg0, dst4, dst5, dst6, dst7);