Lines Matching refs:DUP2_ARG2
80 DUP2_ARG2(__lsx_vdp2_w_h, s1_m, k0_m, s0_m, k0_m, s1_m, s0_m); \
81 DUP2_ARG2(__lsx_vsrari_w, s1_m, VP9_DCT_CONST_BITS, \
84 DUP2_ARG2(__lsx_vdp2_w_h, s3_m, k0_m, s2_m, k0_m, s1_m, s0_m); \
85 DUP2_ARG2(__lsx_vsrari_w, s1_m, VP9_DCT_CONST_BITS, \
117 DUP2_ARG2(__lsx_vpickev_b, res1_m, res0_m, res3_m, res2_m, \
174 DUP2_ARG2(__lsx_vpickev_h, tmp1_m, tmp0_m, tmp3_m, tmp2_m, out0, out1); \
180 DUP2_ARG2(__lsx_vpickev_h, tmp1_m, tmp0_m, tmp3_m, tmp2_m, out2, out3); \
187 DUP2_ARG2(__lsx_vreplvei_h, mask_h, idx1_h, mask_h, idx2_h, c0_m, c1_m); \
208 DUP2_ARG2(__lsx_vsub_h, in1, in3, in7, in5, res0_m, res1_m); \
220 DUP2_ARG2(__lsx_vpickev_h, tmp1_m, tmp0_m, tmp3_m, tmp2_m, tp5_m, tp6_m); \
275 DUP2_ARG2(__lsx_vilvh_h, in3, in0, in2, in1, s0, s1);
290 DUP2_ARG2(__lsx_vilvl_h, in3, in1, in2, in0, s1, s0);
308 DUP2_ARG2(__lsx_vdp2_w_h, s0, k1, s0, k0, tmp0, tmp1);
309 DUP2_ARG2(__lsx_vsrari_w, tmp0, VP9_DCT_CONST_BITS, tmp1,
311 DUP2_ARG2(__lsx_vpickev_h, zero, tmp0, zero, tmp1, s2, s3);
656 DUP2_ARG2(__lsx_vldx, dst, dst_stride, dst, stride2, dst1, dst2);
1036 DUP2_ARG2(__lsx_vadd_h, reg5, reg4, reg3, reg2, vec0, vec1);
1039 DUP2_ARG2(__lsx_vsub_h, reg5, reg4, reg3, reg2, vec0, vec1);
1116 DUP2_ARG2(__lsx_vsub_h, reg0, reg4, reg1, reg5, vec0, vec1);
1119 DUP2_ARG2(__lsx_vsub_h, reg2, reg6, reg3, reg7, vec0, vec1);
1141 DUP2_ARG2(__lsx_vsub_h, reg0, reg4, reg3, reg7, vec0, vec1);
1144 DUP2_ARG2(__lsx_vsub_h, reg1, reg5, reg2, reg6, vec0, vec1);
1288 DUP2_ARG2(__lsx_vld, dst, 0, dst, 16, dst0, dst1);
1289 DUP2_ARG2(__lsx_vld, dst_tmp, 0, dst_tmp, 16, dst2, dst3);