Lines Matching refs:src5
42 __m128i src0, src1, src2, src3, src4, src5, src6, src7;
61 src4, src5, src6, src7);
94 DUP2_ARG3(__lsx_vshuf_b, src4, src4, mask0, src5, src5, mask0,
100 DUP2_ARG3(__lsx_vshuf_b, src4, src4, mask2, src5, src5, mask2,
106 DUP2_ARG3(__lsx_vshuf_b, src4, src4, mask1, src5, src5, mask1,
112 DUP2_ARG3(__lsx_vshuf_b, src4, src4, mask3, src5, src5, mask3,
140 __m128i src0, src1, src2, src3, src4, src5, src6, src7, src8, src9, src10;
155 DUP2_ARG2(__lsx_vldx, src, src_stride, src, src_stride_2x, src5, src6);
157 DUP4_ARG2(__lsx_vilvl_b, src1, src0, src3, src2, src5, src4, src2, src1,
159 DUP2_ARG2(__lsx_vilvl_b, src4, src3, src6, src5, src43_r, src65_r);
214 __m128i src0, src1, src2, src3, src4, src5, src6, src7, src8, src9, src10;
237 src5, src6);
239 DUP4_ARG2(__lsx_vilvl_b, src1, src0, src3, src2, src5, src4, src2, src1,
241 DUP2_ARG2(__lsx_vilvl_b, src4, src3, src6, src5, src43_r, src65_r);
242 DUP4_ARG2(__lsx_vilvh_b, src1, src0, src3, src2, src5, src4, src2, src1,
244 DUP2_ARG2(__lsx_vilvh_b, src4, src3, src6, src5, src43_l, src65_l);
351 __m128i src0, src1, src2, src3, src4, src5, src6, src7, src8;
389 src5, src6);
412 DUP4_ARG3(__lsx_vshuf_b, src5, src5, mask0, src5, src5, mask1, src5,
413 src5, mask2, src5, src5, mask3, vec4, vec5, vec6, vec7);
557 __m128i src0, src1, src2, src3, src4, src5, src6, src7, src8, src9, src10;
617 DUP2_ARG2(__lsx_vld, src, 0, _src, 0, src5, src11);
619 DUP2_ARG2(__lsx_vilvl_b, src5, src4, src2, src5, src10_r, src21_r);
620 DUP2_ARG2(__lsx_vilvh_b, src5, src4, src2, src5, src10_l, src21_l);
821 __m128i src0, src1, src2, src3, src4, src5, src6, mask0, mask1;
845 DUP2_ARG2(__lsx_vldx, src, src_stride, src, src_stride_2x, src5, src6);
867 DUP2_ARG3(__lsx_vshuf_b, src5, src5, mask0, src5, src5, mask1,
916 __m128i src0, src1, src2, src3, src4, src5, src6, src7, src8;
946 src_stride_3x, src, src_stride_4x, src5, src6, src7, src8);
952 DUP4_ARG3(__lsx_vshuf_b, src4, src4, mask0, src4, src4, mask1, src5, src5,
953 mask0, src5, src5, mask1, vec8, vec9, vec10, vec11);
1028 __m128i src0, src1, src2, src3, src4, src5, src6;
1077 src4, src5);
1083 DUP4_ARG3(__lsx_vshuf_b, src5, src5, mask0, src5, src5, mask1, src6,
1162 __m128i src0, src1, src2, src3, src4, src5, src6, src7, src8, src9, src10;
1208 src4, src5);
1214 DUP4_ARG3(__lsx_vshuf_b, src5, src5, mask0, src5, src5, mask1, src6,
1278 DUP2_ARG2(__lsx_vldx, src, src_stride, src, src_stride_2x, src4, src5);
1287 DUP4_ARG3(__lsx_vshuf_b, src9, src5, mask2, src9, src5, mask3, src10,