Lines Matching defs:src2
42 __m128i src0, src1, src2, src3, src4, src5, src6, src7;
59 src0, src1, src2, src3);
66 DUP2_ARG3(__lsx_vshuf_b, src2, src2, mask0, src3, src3, mask0,
72 DUP2_ARG3(__lsx_vshuf_b, src2, src2, mask2, src3, src3, mask2,
78 DUP2_ARG3(__lsx_vshuf_b, src2, src2, mask1, src3, src3, mask1,
84 DUP2_ARG3(__lsx_vshuf_b, src2, src2, mask3, src3, src3, mask3,
140 __m128i src0, src1, src2, src3, src4, src5, src6, src7, src8, src9, src10;
151 DUP2_ARG2(__lsx_vldx, src, src_stride, src, src_stride_2x, src1, src2);
157 DUP4_ARG2(__lsx_vilvl_b, src1, src0, src3, src2, src5, src4, src2, src1,
214 __m128i src0, src1, src2, src3, src4, src5, src6, src7, src8, src9, src10;
232 src1, src2);
239 DUP4_ARG2(__lsx_vilvl_b, src1, src0, src3, src2, src5, src4, src2, src1,
242 DUP4_ARG2(__lsx_vilvh_b, src1, src0, src3, src2, src5, src4, src2, src1,
351 __m128i src0, src1, src2, src3, src4, src5, src6, src7, src8;
384 src1, src2);
397 DUP4_ARG3(__lsx_vshuf_b, src2, src2, mask0, src2, src2, mask1, src2,
398 src2, mask2, src2, src2, mask3, vec8, vec9, vec10, vec11);
557 __m128i src0, src1, src2, src3, src4, src5, src6, src7, src8, src9, src10;
570 DUP2_ARG2(__lsx_vldx, src, src_stride, src, src_stride_2x, src1, src2);
571 DUP2_ARG2(__lsx_vilvl_b, src1, src0, src2, src1, src10_r, src21_r);
572 DUP2_ARG2(__lsx_vilvh_b, src1, src0, src2, src1, src10_l, src21_l);
585 DUP2_ARG2(__lsx_vilvl_b, src3, src2, src4, src3, src32_r, src43_r);
586 DUP2_ARG2(__lsx_vilvh_b, src3, src2, src4, src3, src32_l, src43_l);
618 DUP2_ARG2(__lsx_vldx, src, src_stride, _src, src_stride, src2, src8);
619 DUP2_ARG2(__lsx_vilvl_b, src5, src4, src2, src5, src10_r, src21_r);
620 DUP2_ARG2(__lsx_vilvh_b, src5, src4, src2, src5, src10_l, src21_l);
664 __m128i src0, src1, src2, src3, src4, src6, src7, src8, src9, src10;
679 DUP2_ARG2(__lsx_vldx, src, src_stride, src, src_stride_2x, src1, src2);
681 DUP2_ARG2(__lsx_vilvl_b, src1, src0, src2, src1, src10_r, src21_r);
682 DUP2_ARG2(__lsx_vilvh_b, src1, src0, src2, src1, src10_l, src21_l);
697 DUP2_ARG2(__lsx_vilvl_b, src3, src2, src4, src3, src32_r, src43_r);
698 DUP2_ARG2(__lsx_vilvh_b, src3, src2, src4, src3, src32_l, src43_l);
716 src2 = src4;
756 __m128i src0, src1, src2, src3, src4;
778 src_stride_3x, src, src_stride_4x, src1, src2, src3, src4);
782 DUP4_ARG3(__lsx_vshuf_b, src2, src2, mask0, src2, src2, mask1, src3, src3,
821 __m128i src0, src1, src2, src3, src4, src5, src6, mask0, mask1;
841 DUP2_ARG2(__lsx_vldx, src, src_stride, src, src_stride_2x, src1, src2);
851 DUP2_ARG3(__lsx_vshuf_b, src2, src2, mask0, src2, src2, mask1,
916 __m128i src0, src1, src2, src3, src4, src5, src6, src7, src8;
943 src_stride_3x, src, src_stride_4x, src1, src2, src3, src4);
950 DUP4_ARG3(__lsx_vshuf_b, src2, src2, mask0, src2, src2, mask1, src3, src3,
1028 __m128i src0, src1, src2, src3, src4, src5, src6;
1055 src1, src2);
1062 DUP2_ARG3(__lsx_vshuf_b, src2, src2, mask0, src2, src2, mask1,
1162 __m128i src0, src1, src2, src3, src4, src5, src6, src7, src8, src9, src10;
1189 src1, src2);
1194 DUP2_ARG3(__lsx_vshuf_b, src2, src2, mask0, src2, src2, mask1, vec4, vec5);
1263 DUP2_ARG2(__lsx_vldx, src, src_stride, src, src_stride_2x, src1, src2);
1266 DUP2_ARG3(__lsx_vshuf_b, src2, src1, mask2, src2, src1, mask3, vec2, vec3);