Lines Matching defs:reg1
64 __m128i reg0, reg1, reg2, reg3;
69 reg1 = __lsx_vldrepl_w(src0_ptr + src_stride, 0);
73 DUP2_ARG2(__lsx_vilvl_w, reg1, reg0, reg3, reg2, tmp0, tmp1);
76 reg1 = __lsx_vldrepl_w(src0_ptr + src_stride, 0);
79 DUP2_ARG2(__lsx_vilvl_w, reg1, reg0, reg3, reg2, tmp0, tmp1);
113 reg1 = __lsx_vldrepl_w(src0_ptr + src_stride, 0);
116 src0 = __lsx_vilvl_w(reg1, reg0);
150 __m128i reg0, reg1, reg2, reg3;
154 reg1 = __lsx_vldrepl_d(src0_ptr + src_stride, 0);
157 DUP2_ARG2(__lsx_vilvl_d, reg1, reg0, reg3, reg2, src0, src1);
160 reg1 = __lsx_vldrepl_d(src0_ptr + src_stride, 0);
163 DUP2_ARG2(__lsx_vilvl_d, reg1, reg0, reg3, reg2, src2, src3);
206 reg1 = __lsx_vldrepl_d(src0_ptr + src_stride, 0);
207 src0 = __lsx_vilvl_d(reg1, reg0);
246 __m128i reg0, reg1, reg2, reg3;
250 reg1 = __lsx_vldrepl_d(src0_ptr + src_stride, 0);
253 DUP2_ARG2(__lsx_vilvl_d, reg1, reg0, reg3, reg2, src0, src1);
256 reg1 = __lsx_vldrepl_d(src0_ptr + src_stride, 0);
259 DUP2_ARG2(__lsx_vilvl_d, reg1, reg0, reg3, reg2, src2, src3);
294 reg1 = __lsx_vldrepl_d(src0_ptr + src_stride, 0);
295 src0 = __lsx_vilvl_d(reg1, reg0);
1507 __m128i reg0, reg1, reg2, reg3;
1609 reg1 = __lsx_vldrepl_d(src1_ptr + src2_stride, 0);
1610 dsth0 = __lsx_vilvl_d(reg1, reg0);
1612 reg1 = __lsx_vldrepl_d(src1_ptr + src2_stride_3x, 0);
1613 dsth1 = __lsx_vilvl_d(reg1, reg0);
1616 reg1 = __lsx_vldrepl_d(src1_ptr + src2_stride, 0);
1617 dsth2 = __lsx_vilvl_d(reg1, reg0);
1619 reg1 = __lsx_vldrepl_d(src1_ptr + src2_stride_3x, 0);
1620 dsth3 = __lsx_vilvl_d(reg1, reg0);
1642 reg1 = __lsx_vldrepl_w(src1_ptr + src2_stride, 8);
1645 DUP2_ARG2(__lsx_vilvl_w, reg1, reg0, reg3, reg2, tmp0, tmp1);
1650 reg1 = __lsx_vldrepl_w(src1_ptr + src2_stride, 8);
1653 DUP2_ARG2(__lsx_vilvl_w, reg1, reg0, reg3, reg2, tmp0, tmp1);