Lines Matching refs:q2
83 @ Input columns: q0 q1 q2 q3
84 @ Output columns: q0 q1 q2 q3
88 vadd.i16 q12, q0, q2 @ temp1 = src[0] + src[2]
90 vsub.i16 q13, q0, q2 @ temp2 = src[0] - src[2]
111 vhadd.s16 q2, q9, q11 @ dst[2] = (t2 + t4) >> 1
117 vshr.s16 q2, q2, #(\rshift - 1) @ dst[2] >>= (rshift - 1)
144 vshl.i16 q15, q2, #4 @ t3|t4 = 16 * (src[16]|src[48])
145 vswp d4, d5 @ q2 = src[48]|src[16]
151 vmla.i16 q15, q2, d0[1] @ t3|t4 += 6 * (src[48]|src[16])
166 vshl.i16 q2, q3, #2 @ temp1|temp2 = 4 * (src[56]|src[24])
169 vadd.i16 q8, q8, q2 @ t1|t2 += temp1|temp2
203 vadd.i16 q2, q15, q11 @ line[5,4] = t7|t8 + 1
211 vhsub.s16 q2, q2, q9 @ line[5,4] = (t7|t8 - t3|t4 + 1) >> 1
214 vhsub.s16 q2, q11, q9 @ line[5,4] = (t7|t8 - t3|t4) >> 1
220 vshr.s16 q10, q2, #(\rshift - 1)
244 vmul.i16 q2, q10, q0 @ t4 = 6/2 * src[16]
254 vsub.i16 q2, q2, q3 @ t4 = 6/2 * src[16] - 16/2 * src[48]
265 @ q2 old t4
300 vadd.i16 q13, q12, q2 @ t6 = t2 + t4
301 vsub.i16 q2, q12, q2 @ t7 = t2 - t4
322 @ t7half q2
352 vadd.i16 q15, q2, q9 @ q15 = t7half + t3
364 vhadd.s16 q15, q2, q15 @ q15 = (t7half + t7half + t3) >> 1
365 vsub.i16 q9, q2, q9 @ q9 = t7half - t3 + 1
378 vhadd.s16 q13, q2, q9 @ q9 = (t7half + t7half - t3 + 1) >> 1
379 @ unused: q12, q2, q9
432 vld1.64 {q2-q3}, [r2,:128]
434 transpose16 q0, q1, q2, q3 @ transpose rows to columns
468 transpose16 q0, q1, q2, q3 @ turn columns into rows
473 @ row[2] q2
498 vaddw.u8 q2, q2, d30 @ line[2] += dest[2]
503 vqmovun.s16 d2, q2 @ line[2]
531 @ dst[2] = q2
534 transpose16 q0, q1, q2, q3 @ Transpose rows (registers) into columns
581 vmov.i16 q2, #\add @ t1|t2 will accumulate here
586 vmla.i16 q2, q13, q8 @ t1|t2 = 17 * (temp1|temp2) + add
590 vadd.i16 q0, q2, q3 @ dst[0,2] = (t1|t2 + t3|t4)
591 vsub.i16 q1, q2, q3 @ dst[3,1] = (t1|t2 - t3|t4)
791 @ q2 [hv] src[stride]
863 vext.16 q2, q0, q1, #2
1154 vaddw.u8 q2, q1, d0
1156 vqmovun.s16 d0, q2
1190 vshll.u8 q2, d5, #1 @ 2*P3
1252 vtrn.8 q1, q2
1258 vmovl.u8 q2, d5 @ P4, P8
1263 vmls.i16 q3, q2, d0[0] @ 2*P1-5*P2+5*P3-2*P4, 2*P5-5*P6+5*P7-2*P8
1297 vqmovun.s16 d0, q2
1329 vshll.u8 q2, d5, #1 @ 2*P3
1337 vmls.i16 q2, q3, d0[1] @ 2*P3-5*P4
1343 vmla.i16 q2, q1, d0[1] @ 2*P3-5*P4+5*P5
1345 vmls.i16 q2, q11, d0[0] @ 2*P3-5*P4+5*P5-2*P6
1350 vrshr.s16 q2, q2, #3
1352 vabs.s16 q15, q2 @ a0
1353 vshr.s16 q2, q2, #8 @ a0_sign
1356 vsub.i16 q2, q13, q2 @ clip_sign - a0_sign
1374 vmls.i16 q3, q0, q2 @ invert d depending on clip_sign & a0_sign, or zero it if they match, and accumulate into P4
1375 vmla.i16 q1, q0, q2 @ invert d depending on clip_sign & a0_sign, or zero it if they match, and accumulate into P5
1406 vtrn.8 q1, q2 @ P1[0], P1[1], P3[0]... P1[2], P1[3], P3[2]... P2[0], P2[1], P4[0]... P2[2], P2[3], P4[2]...
1426 vmovl.u8 q2, d5 @ P4
1431 vsub.i16 q12, q2, q3 @ P4-P5
1432 vmls.i16 q1, q2, d0[1] @ 2*P3-5*P4
1436 vmls.i16 q10, q2, d0[0] @ 2*P1-5*P2+5*P3-2*P4
1467 vmls.i16 q2, q0, q1 @ invert d depending on clip_sign & a0_sign, or zero it if they match, and accumulate into P4
1469 vqmovun.s16 d0, q2
1495 vld1.64 {q2}, [r3 :128], r1 @ P1
1507 vshll.u8 q2, d5, #1 @ 2*P1[8..15]
1515 vmls.i16 q2, q3, d0[1] @ 2*P1[8..15]-5*P2[8..15]
1526 vmla.i16 q2, q15, d0[1] @ 2*P1[8..15]-5*P2[8..15]+5*P3[8..15]
1538 vmls.i16 q2, q9, d0[0] @ 2*P1[8..15]-5*P2[8..15]+5*P3[8..15]-2*P4[8..15]
1545 vrshr.s16 q2, q2, #3
1553 vabs.s16 q2, q2 @ a1[8..15]
1560 vcge.s16 q12, q2, q10 @ test a1[8..15] >= a2[8.15]
1562 vbsl q12, q10, q2 @ a3[8..15]
1563 vabs.s16 q2, q3 @ a0[0..7]
1567 vcge.s16 q15, q2, q13 @ test a0[0..7] >= pq
1569 vqsub.u16 q15, q2, q4 @ a0[0..7] >= a3[0..7] ? a0[0..7]-a3[0..7] : 0 (a0 > a3 in all cases where filtering is enabled, so makes more sense to subtract this way round than the opposite and then taking the abs)
1570 vcge.s16 q2, q4, q2 @ test a3[0..7] >= a0[0..7]
1575 vorr q2, q10, q2 @ test clip[0..7] == 0 || a0[0..7] >= pq || a3[0..7] >= a0[0..7]
1584 vshl.i64 q2, q2, #16
1588 vshr.s64 q2, q2, #48
1594 vorr q2, q10, q2
1598 vbic q2, q12, q2 @ set each d[0..7] to zero if it should not be filtered because clip[0..7] == 0 || a0[0..7] >= pq (a3 > a0 case already zeroed by saturating sub)
1602 vmls.i16 q14, q2, q3 @ invert d[0..7] depending on clip_sign[0..7] & a0_sign[0..7], or zero it if they match, and accumulate into P4[0..7]
1607 vmla.i16 q6, q2, q3 @ invert d[0..7] depending on clip_sign[0..7] & a0_sign[0..7], or zero it if they match, and accumulate into P5[0..7]
1614 vst1.64 {q2}, [r3 :128], r1
1679 vshll.u8 q2, d5, #1 @ 2*P1[8..15]
1687 vmls.i16 q2, q14, d0[1] @ 2*P1[8..15]-5*P2[8..15]
1695 vmla.i16 q2, q1, d0[1] @ 2*P1[8..15]-5*P2[8..15]+5*P3[8..15]
1706 vmls.i16 q2, q6, d0[0] @ 2*P1[8..15]-5*P2[8..15]+5*P3[8..15]-2*P4[8..15]
1712 vrshr.s16 q2, q2, #3
1718 vabs.s16 q2, q2 @ a1[8..15]
1728 vcge.s16 q3, q2, q12 @ test a1[8..15] >= a2[8.15]
1731 vbsl q3, q12, q2 @ a3[8..15]
1732 vabs.s16 q2, q14 @ a0[0..7]
1741 vcge.s16 q9, q2, q9 @ test a0[0..7] >= pq
1743 vqsub.u16 q14, q2, q13 @ a0[0..7] >= a3[0..7] ? a0[0..7]-a3[0..7] : 0 (a0 > a3 in all cases where filtering is enabled, so makes more sense to subtract this way round than the opposite and then taking the abs)
1744 vcge.s16 q2, q13, q2 @ test a3[0..7] >= a0[0..7]
1751 vorr q2, q9, q2 @ test clip[0..7] == 0 || a0[0..7] >= pq || a3[0..7] >= a0[0..7]
1758 vcge.s16 q2, q0, q11
1760 vbsl q2, q11, q0 @ FFMIN(d[0..7], clip[0..7])
1765 vbic q2, q2, q9 @ set each d[0..7] to zero if it should not be filtered because clip[0..7] == 0 || a0[0..7] >= pq (a3 > a0 case already zeroed by saturating sub)
1767 vmls.i16 q5, q2, q1 @ invert d[0..7] depending on clip_sign[0..7] & a0_sign[0..7], or zero it if they match, and accumulate into P4
1769 vmla.i16 q4, q2, q1 @ invert d[0..7] depending on clip_sign[0..7] & a0_sign[0..7], or zero it if they match, and accumulate into P5