Lines Matching refs:fd
197 static void pa4s2_readbegin_epp (int fd, u_char reg);
198 static u_char pa4s2_readbyte_epp (int fd);
199 static void pa4s2_readend_epp (int fd);
200 static void pa4s2_readbegin_uni (int fd, u_char reg);
201 static u_char pa4s2_readbyte_uni (int fd);
202 static void pa4s2_readend_uni (int fd);
203 static void pa4s2_readbegin_nib (int fd, u_char reg);
204 static u_char pa4s2_readbyte_nib (int fd);
205 static void pa4s2_readend_nib (int fd);
206 static void pa4s2_writebyte_any (int fd, u_char reg, u_char val);
207 static int pa4s2_enable (int fd, u_char * prelock);
208 static int pa4s2_disable (int fd, u_char * prelock);
209 static int pa4s2_close (int fd, SANE_Status * status);
508 DBG (4, "pa4s2_open: open dev `%s` as fd %u\n", dev, n);
517 #define inbyte0(fd) ieee1284_read_data(pplist.portv[fd]);
518 #define inbyte1(fd) (ieee1284_read_status(pplist.portv[fd]) ^ S1284_INVERTED)
519 #define inbyte2(fd) (ieee1284_read_control(pplist.portv[fd]) ^ C1284_INVERTED)
520 static u_char inbyte4(int fd)
523 ieee1284_epp_read_data(pplist.portv[fd], 0, &val, 1);
527 #define outbyte0(fd,val) ieee1284_write_data(pplist.portv[fd], val)
528 #define outbyte1(fd,val) /* ieee1284_write_status(pplist.portv[fd], (val) ^ S1284_INVERTED) */
529 #define outbyte2(fd,val) ieee1284_write_control(pplist.portv[fd], (val) ^ C1284_INVERTED)
531 static void outbyte3(int fd, u_char val)
533 ieee1284_epp_write_addr (pplist.portv[fd], 0, (char *)&val, 1);
538 #define inbyte0(fd) sanei_inb(port[fd].base)
539 #define inbyte1(fd) sanei_inb(port[fd].base + 1)
540 #define inbyte2(fd) sanei_inb(port[fd].base + 2)
541 #define inbyte4(fd) sanei_inb(port[fd].base + 4)
543 #define outbyte0(fd,val) sanei_outb(port[fd].base, val)
544 #define outbyte1(fd,val) sanei_outb(port[fd].base + 1, val)
545 #define outbyte2(fd,val) sanei_outb(port[fd].base + 2, val)
546 #define outbyte3(fd,val) sanei_outb(port[fd].base + 3, val)
552 pa4s2_readbegin_epp (int fd, u_char reg)
557 (int) reg, pplist.portv[fd]->name);
560 (int) reg, port[fd].base);
563 outbyte0 (fd, 0x20);
564 outbyte2 (fd, 0x04);
565 outbyte2 (fd, 0x06);
566 outbyte2 (fd, 0x04);
567 outbyte3 (fd, reg + 0x18);
572 pa4s2_readbyte_epp (int fd)
575 u_char val = inbyte4 (fd);
579 (int) val, pplist.portv[fd]->name);
582 (int) val, port[fd].base);
590 pa4s2_readend_epp (int fd)
595 outbyte2 (fd, 0x04);
596 outbyte2 (fd, 0x00);
597 outbyte2 (fd, 0x04);
602 pa4s2_readbegin_uni (int fd, u_char reg)
607 (int) reg, pplist.portv[fd]->name);
610 (int) reg, port[fd].base);
613 outbyte0 (fd, reg | 0x58);
614 outbyte2 (fd, 0x04);
615 outbyte2 (fd, 0x06);
616 outbyte2 (fd, 0x04);
617 outbyte2 (fd, 0x04);
622 pa4s2_readbyte_uni (int fd)
626 outbyte2 (fd, 0x05);
627 val = inbyte2(fd);
630 val |= (inbyte1(fd) >> 3);
631 outbyte2 (fd, 0x04);
635 (int) val, pplist.portv[fd]->name);
638 (int) val, port[fd].base);
645 pa4s2_readend_uni (int fd)
648 DBG (6, "pa4s2_readend_uni: end of reading sequence for fd %d\n", fd);
653 pa4s2_readbegin_nib (int fd, u_char reg)
658 (int) reg, pplist.portv[fd]->name);
661 (int) reg, port[fd].base);
665 outbyte0 (fd, reg | 0x18);
666 outbyte2 (fd, 0x04);
667 outbyte2 (fd, 0x06);
668 outbyte2 (fd, 0x04);
669 outbyte2 (fd, 0x04);
674 pa4s2_readbyte_nib (int fd)
679 outbyte2 (fd, 0x05);
680 val = inbyte1(fd);
682 outbyte0 (fd, 0x58);
683 val |= inbyte1(fd) & 0xF0;
685 outbyte0 (fd, 0x00);
686 outbyte2 (fd, 0x04);
690 (int) val, pplist.portv[fd]->name);
693 (int) val, port[fd].base);
701 pa4s2_readend_nib (int fd)
703 DBG (6, "pa4s2_readend_nib: end of reading sequence for fd %d\n", fd);
707 pa4s2_writebyte_any (int fd, u_char reg, u_char val)
717 " in reg %u to '%s'\n", (int) val, (int) reg, pplist.portv[fd]->name);
720 " in reg %u at 0x%03lx\n", (int) val, (int) reg, port[fd].base);
723 outbyte0 (fd, reg | 0x10);
724 outbyte2 (fd, 0x04);
725 outbyte2 (fd, 0x06);
726 outbyte2 (fd, 0x06);
727 outbyte2 (fd, 0x06);
728 outbyte2 (fd, 0x06);
729 outbyte2 (fd, 0x04);
730 outbyte2 (fd, 0x04);
731 outbyte0 (fd, val);
732 outbyte2 (fd, 0x05);
733 outbyte2 (fd, 0x05);
734 outbyte2 (fd, 0x05);
735 outbyte2 (fd, 0x04);
736 outbyte2 (fd, 0x04);
737 outbyte2 (fd, 0x04);
738 outbyte2 (fd, 0x04);
742 pa4s2_enable (int fd, u_char * prelock)
746 result = ieee1284_claim (pplist.portv[fd]);
756 prelock[0] = inbyte0 (fd);
757 prelock[1] = inbyte1 (fd);
758 prelock[2] = inbyte2 (fd);
759 outbyte2 (fd, (prelock[2] & 0x0F) | 0x04);
764 outbyte0 (fd, 0x15);
765 outbyte0 (fd, 0x95);
766 outbyte0 (fd, 0x35);
767 outbyte0 (fd, 0xB5);
768 outbyte0 (fd, 0x55);
769 outbyte0 (fd, 0xD5);
770 outbyte0 (fd, 0x75);
771 outbyte0 (fd, 0xF5);
772 outbyte0 (fd, 0x01);
773 outbyte0 (fd, 0x81);
779 pa4s2_disable (int fd, u_char * prelock)
787 outbyte0 (fd, 0x00);
788 outbyte2 (fd, 0x04);
789 outbyte2 (fd, 0x06);
790 outbyte2 (fd, 0x04);
794 outbyte2 (fd, prelock[2] & 0x0F);
796 outbyte0 (fd, 0x15);
797 outbyte0 (fd, 0x95);
798 outbyte0 (fd, 0x35);
799 outbyte0 (fd, 0xB5);
800 outbyte0 (fd, 0x55);
801 outbyte0 (fd, 0xD5);
802 outbyte0 (fd, 0x75);
803 outbyte0 (fd, 0xF5);
804 outbyte0 (fd, 0x00);
805 outbyte0 (fd, 0x80);
807 outbyte0 (fd, prelock[0]);
808 outbyte1 (fd, prelock[1]);
809 outbyte2 (fd, prelock[2]);
812 ieee1284_release (pplist.portv[fd]);
822 pa4s2_close (int fd, SANE_Status * status)
827 DBG (4, "pa4s2_close: fd=%d\n", fd);
830 DBG (6, "pa4s2_close: this is port '%s'\n", pplist.portv[fd]->name);
832 DBG (6, "pa4s2_close: this is port 0x%03lx\n", port[fd].base);
837 if (port[fd].enabled == SANE_TRUE)
841 pa4s2_disable (fd, port[fd].prelock);
847 if ((result = ieee1284_close(pplist.portv[fd])) < 0)
849 if (sanei_ioperm (port[fd].base, 5, 0))
855 pplist.portv[fd]->name, pa4s2_libieee1284_errorstr(result));
857 DBG (1, "pa4s2_close: can't free port 0x%03lx\n", port[fd].base);
868 port[fd].in_use = SANE_FALSE;
928 sanei_pa4s2_scsi_pp_get_status(int fd, u_char *status)
934 DBG (6, "sanei_pa4s2_scsi_pp_get_status: called for fd %d\n",
935 fd);
938 if ((fd < 0) || (fd >= pplist.portc))
940 if ((fd < 0) || (fd >= NELEMS (port)))
944 DBG (2, "sanei_pa4s2_scsi_pp_get_status: invalid fd %d\n", fd);
951 if (port[fd].in_use == SANE_FALSE)
957 pplist.portv[fd]->name);
960 port[fd].base);
968 if (port[fd].enabled == SANE_FALSE)
974 pplist.portv[fd]->name);
977 port[fd].base);
985 outbyte2 (fd, 0x4);
986 stat = inbyte1 (fd)^0x80;
999 sanei_pa4s2_scsi_pp_reg_select (int fd, int reg)
1004 if ((fd < 0) || (fd >= pplist.portc))
1006 if ((fd < 0) || (fd >= NELEMS (port)))
1010 DBG (2, "sanei_pa4s2_scsi_pp_reg_select: invalid fd %d\n", fd);
1017 if (port[fd].in_use == SANE_FALSE)
1023 pplist.portv[fd]->name);
1026 port[fd].base);
1034 if (port[fd].enabled == SANE_FALSE)
1040 pplist.portv[fd]->name);
1043 port[fd].base);
1053 (int) reg, pplist.portv[fd]->name);
1056 (int) reg, (u_long)port[fd].base);
1059 outbyte0 (fd, reg | 0x58);
1060 outbyte2 (fd, 0x04);
1061 outbyte2 (fd, 0x06);
1062 outbyte2 (fd, 0x04);
1063 outbyte2 (fd, 0x04);
1074 sanei_pa4s2_scsi_pp_open (const char *dev, int *fd)
1085 if ((*fd = pa4s2_open (dev, &status)) == -1)
1094 DBG (6, "sanei_pa4s2_scsi_pp_open: connected to device using fd %u\n", *fd);
1098 if (sanei_pa4s2_enable (*fd, SANE_TRUE)!=SANE_STATUS_GOOD)
1107 if (sanei_pa4s2_scsi_pp_get_status(*fd, &val)!=SANE_STATUS_GOOD)
1110 sanei_pa4s2_enable (*fd, SANE_FALSE);
1118 sanei_pa4s2_enable (*fd, SANE_FALSE);
1122 if (sanei_pa4s2_enable (*fd, SANE_FALSE)!=SANE_STATUS_GOOD)
1137 sanei_pa4s2_open (const char *dev, int *fd)
1148 if ((*fd = pa4s2_open (dev, &status)) == -1)
1157 DBG (6, "sanei_pa4s2_open: connected to device using fd %u\n", *fd);
1161 sanei_pa4s2_enable (*fd, SANE_TRUE);
1165 sanei_pa4s2_readbegin (*fd, 0);
1167 sanei_pa4s2_readbyte (*fd, &asic);
1169 sanei_pa4s2_readend (*fd);
1191 sanei_pa4s2_enable (*fd, SANE_FALSE);
1194 sanei_pa4s2_close (*fd);
1202 sanei_pa4s2_enable (*fd, SANE_FALSE);
1206 while (port[*fd].mode <= PA4S2_MODE_EPP)
1209 if ((port[*fd].mode == PA4S2_MODE_UNI) &&
1214 port[*fd].mode++;
1219 if ((port[*fd].mode == PA4S2_MODE_EPP) &&
1227 DBG (5, "sanei_pa4s2_open: trying mode %u\n", port[*fd].mode);
1229 sanei_pa4s2_enable (*fd, SANE_TRUE);
1231 sanei_pa4s2_readbegin (*fd, 0);
1233 sanei_pa4s2_readbyte (*fd, &val);
1238 sanei_pa4s2_readend (*fd);
1239 sanei_pa4s2_enable (*fd, SANE_FALSE);
1247 sanei_pa4s2_readend (*fd);
1248 sanei_pa4s2_enable (*fd, SANE_FALSE);
1252 port[*fd].mode++;
1256 port[*fd].mode--;
1258 if ((port[*fd].mode == PA4S2_MODE_UNI) &&
1261 port[*fd].mode--;
1264 DBG (5, "sanei_pa4s2_open: using mode %u\n", port[*fd].mode);
1273 sanei_pa4s2_close (int fd)
1280 DBG (4, "sanei_pa4s2_close: fd = %d\n", fd);
1283 if ((fd < 0) || (fd >= pplist.portc))
1285 if ((fd < 0) || (fd >= NELEMS (port)))
1289 DBG (2, "sanei_pa4s2_close: fd %d is invalid\n", fd);
1295 if (port[fd].in_use == SANE_FALSE)
1300 DBG (6, "sanei_pa4s2_close: port is '%s'\n", pplist.portv[fd]->name);
1302 DBG (6, "sanei_pa4s2_close: port is 0x%03lx\n", port[fd].base);
1311 if (pa4s2_close (fd, &status) == -1)
1324 sanei_pa4s2_enable (int fd, int enable)
1329 DBG (4, "sanei_pa4s2_enable: called for fd %d with value %d\n",
1330 fd, enable);
1333 if ((fd < 0) || (fd >= pplist.portc))
1335 if ((fd < 0) || (fd >= NELEMS (port)))
1339 DBG (2, "sanei_pa4s2_enable: fd %d is invalid\n", fd);
1346 if (port[fd].in_use == SANE_FALSE)
1351 DBG (6, "sanei_pa4s2_close: port is '%s'\n", pplist.portv[fd]->name);
1353 DBG (6, "sanei_pa4s2_close: port is 0x%03lx\n", port[fd].base);
1371 if ((unsigned int) enable == port[fd].enabled)
1386 DBG (4, "sanei_pa4s2_enable: enable port '%s'\n", pplist.portv[fd]->name);
1388 DBG (4, "sanei_pa4s2_enable: enable port 0x%03lx\n", port[fd].base);
1394 if (sanei_ioperm (port[fd].base, 5, 1))
1397 " 0x%03lx\n", port[fd].base);
1399 DBG (5, "sanei_pa4s2_enable:: marking port[%d] as unused\n", fd);
1400 port[fd].in_use = SANE_FALSE;
1407 if (pa4s2_enable (fd, port[fd].prelock) != 0)
1421 pplist.portv[fd]->name);
1423 DBG (4, "sanei_pa4s2_enable: disable port 0x%03lx\n", port[fd].base);
1426 pa4s2_disable (fd, port[fd].prelock);
1430 port[fd].enabled = enable;
1438 sanei_pa4s2_readbegin (int fd, u_char reg)
1443 DBG (4, "sanei_pa4s2_readbegin: called for fd %d and register %u\n",
1444 fd, (int) reg);
1447 if ((fd < 0) || (fd >= pplist.portc))
1449 if ((fd < 0) || (fd >= NELEMS (port)))
1453 DBG (2, "sanei_pa4s2_readbegin: invalid fd %d\n", fd);
1460 if (port[fd].in_use == SANE_FALSE)
1465 DBG (6, "sanei_pa4s2_close: port is '%s'\n", pplist.portv[fd]->name);
1467 DBG (6, "sanei_pa4s2_close: port is 0x%03lx\n", port[fd].base);
1475 if (port[fd].enabled == SANE_FALSE)
1480 DBG (6, "sanei_pa4s2_close: port is '%s'\n", pplist.portv[fd]->name);
1482 DBG (6, "sanei_pa4s2_close: port is 0x%03lx\n", port[fd].base);
1490 switch (port[fd].mode)
1496 pa4s2_readbegin_epp (fd, reg);
1502 pa4s2_readbegin_uni (fd, reg);
1508 pa4s2_readbegin_nib (fd, reg);
1516 DBG (6, "sanei_pa4s2_close: port is '%s'\n", pplist.portv[fd]->name);
1518 DBG (6, "sanei_pa4s2_close: port is 0x%03lx\n", port[fd].base);
1532 sanei_pa4s2_readbyte (int fd, u_char * val)
1537 DBG (4, "sanei_pa4s2_readbyte: called with fd %d\n", fd);
1548 if ((fd < 0) || (fd >= pplist.portc))
1550 if ((fd < 0) || (fd >= NELEMS (port)))
1554 DBG (2, "sanei_pa4s2_readbyte: invalid fd %d\n", fd);
1560 if (port[fd].in_use == SANE_FALSE)
1565 DBG (6, "sanei_pa4s2_close: port is '%s'\n", pplist.portv[fd]->name);
1567 DBG (6, "sanei_pa4s2_close: port is 0x%03lx\n", port[fd].base);
1575 if (port[fd].enabled == SANE_FALSE)
1580 DBG (6, "sanei_pa4s2_close: port is '%s'\n", pplist.portv[fd]->name);
1582 DBG (6, "sanei_pa4s2_close: port is 0x%03lx\n", port[fd].base);
1596 switch (port[fd].mode)
1602 *val = pa4s2_readbyte_epp (fd);
1609 *val = pa4s2_readbyte_uni (fd);
1616 *val = pa4s2_readbyte_nib (fd);
1626 port[fd].mode);
1645 sanei_pa4s2_readend (int fd)
1650 DBG (4, "sanei_pa4s2_readend: called for fd %d\n", fd);
1653 if ((fd < 0) || (fd >= pplist.portc))
1655 if ((fd < 0) || (fd >= NELEMS (port)))
1659 DBG (2, "sanei_pa4s2_readend: invalid fd %d\n", fd);
1666 if (port[fd].in_use == SANE_FALSE)
1671 DBG (6, "sanei_pa4s2_close: port is '%s'\n", pplist.portv[fd]->name);
1673 DBG (6, "sanei_pa4s2_close: port is 0x%03lx\n", port[fd].base);
1681 if (port[fd].enabled == SANE_FALSE)
1686 DBG (6, "sanei_pa4s2_close: port is '%s'\n", pplist.portv[fd]->name);
1688 DBG (6, "sanei_pa4s2_close: port is 0x%03lx\n", port[fd].base);
1702 switch (port[fd].mode)
1708 pa4s2_readend_epp (fd);
1715 pa4s2_readend_uni (fd);
1722 pa4s2_readend_nib (fd);
1732 port[fd].mode);
1748 sanei_pa4s2_writebyte (int fd, u_char reg, u_char val)
1753 DBG (4, "sanei_pa4s2_writebyte: called for fd %d, reg %u and val %u\n",
1754 fd, (int) reg, (int) val);
1757 if ((fd < 0) || (fd >= pplist.portc))
1759 if ((fd < 0) || (fd >= NELEMS (port)))
1763 DBG (2, "sanei_pa4s2_writebyte: invalid fd %d\n", fd);
1770 if (port[fd].in_use == SANE_FALSE)
1775 DBG (6, "sanei_pa4s2_close: port is '%s'\n", pplist.portv[fd]->name);
1777 DBG (6, "sanei_pa4s2_close: port is 0x%03lx\n", port[fd].base);
1785 if (port[fd].enabled == SANE_FALSE)
1790 DBG (6, "sanei_pa4s2_close: port is '%s'\n", pplist.portv[fd]->name);
1792 DBG (6, "sanei_pa4s2_close: port is 0x%03lx\n", port[fd].base);
1800 switch (port[fd].mode)
1808 pa4s2_writebyte_any (fd, reg, val);
1816 port[fd].mode);
1872 sanei_pa4s2_open (const char *dev, int *fd)
1877 if (fd)
1878 *fd = -1;
1894 sanei_pa4s2_close (int fd)
1899 DBG (4, "sanei_pa4s2_close: called for fd %d\n", fd);
1900 DBG (2, "sanei_pa4s2_close: fd %d is invalid\n", fd);
1911 sanei_pa4s2_enable (int fd, int enable)
1916 DBG (4, "sanei_pa4s2_enable: called for fd %d with value=%d\n",
1917 fd, enable);
1918 DBG (2, "sanei_pa4s2_enable: fd %d is invalid\n", fd);
1932 sanei_pa4s2_readbegin (int fd, u_char reg)
1937 DBG (4, "sanei_pa4s2_readbegin: called for fd %d and register %d\n",
1938 fd, (int) reg);
1939 DBG (2, "sanei_pa4s2_readbegin: fd %d is invalid\n", fd);
1951 sanei_pa4s2_readbyte (int fd, u_char * val)
1959 DBG (4, "sanei_pa4s2_readbyte: called for fd %d\n", fd);
1960 DBG (2, "sanei_pa4s2_readbyte: fd %d is invalid\n", fd);
1969 sanei_pa4s2_readend (int fd)
1974 DBG (4, "sanei_pa4s2_readend: called for fd %d\n", fd);
1975 DBG (2, "sanei_pa4s2_readend: fd %d is invalid\n", fd);
1985 sanei_pa4s2_writebyte (int fd, u_char reg, u_char val)
1990 DBG (4, "sanei_pa4s2_writebyte: called for fd %d and register %d, "
1991 "value = %u\n", fd, (int) reg, (int) val);
1992 DBG (2, "sanei_pa4s2_writebyte: fd %d is invalid\n", fd);
2037 sanei_pa4s2_scsi_pp_get_status(int fd, u_char *status)
2040 DBG (4, "sanei_pa4s2_scsi_pp_get_status: fd=%d, status=%p\n",
2041 fd, (void *) status);
2047 sanei_pa4s2_scsi_pp_reg_select (int fd, int reg)
2050 DBG (4, "sanei_pa4s2_scsi_pp_reg_select: fd=%d, reg=%d\n",
2051 fd, reg);
2057 sanei_pa4s2_scsi_pp_open (const char *dev, int *fd)
2060 DBG (4, "sanei_pa4s2_scsi_pp_open: dev=%s, fd=%p\n",
2061 dev, (void *) fd);