Lines Matching refs:dev
259 #define M1015_DISPLAY_REGS(dev, msg) Mustek_PP_1015_display_regs(dev, msg)
262 #define M1015_DISPLAY_REGS(dev, msg)
339 Mustek_PP_1015_display_regs(Mustek_PP_CIS_dev * dev, const char* info)
379 Mustek_PP_1015_show_val (dev->CIS.regs.in_regs[0]),
380 Mustek_PP_1015_show_val (dev->CIS.regs.in_regs[1]),
381 Mustek_PP_1015_show_val (dev->CIS.regs.in_regs[2]),
382 Mustek_PP_1015_show_val (dev->CIS.regs.in_regs[3]),
383 Mustek_PP_1015_show_val (dev->CIS.regs.out_regs[0][0]),
384 Mustek_PP_1015_show_val (dev->CIS.regs.out_regs[0][1]),
385 Mustek_PP_1015_show_val (dev->CIS.regs.out_regs[0][2]),
386 Mustek_PP_1015_show_val (dev->CIS.regs.out_regs[0][3]),
387 Mustek_PP_1015_show_val (dev->CIS.regs.out_regs[1][0]),
388 Mustek_PP_1015_show_val (dev->CIS.regs.out_regs[1][1]),
389 Mustek_PP_1015_show_val (dev->CIS.regs.out_regs[1][2]),
390 Mustek_PP_1015_show_val (dev->CIS.regs.out_regs[1][3]),
391 Mustek_PP_1015_show_val (dev->CIS.regs.out_regs[2][0]),
392 Mustek_PP_1015_show_val (dev->CIS.regs.out_regs[2][1]),
393 Mustek_PP_1015_show_val (dev->CIS.regs.out_regs[2][2]),
394 Mustek_PP_1015_show_val (dev->CIS.regs.out_regs[2][3]),
395 Mustek_PP_1015_show_val (dev->CIS.regs.out_regs[3][0]),
396 Mustek_PP_1015_show_val (dev->CIS.regs.out_regs[3][1]),
397 Mustek_PP_1015_show_val (dev->CIS.regs.out_regs[3][2]),
398 Mustek_PP_1015_show_val (dev->CIS.regs.out_regs[3][3]),
399 Mustek_PP_1015_show_val (dev->CIS.regs.channel),
400 (dev->CIS.regs.channel == 0x80 ? "RED" :
401 (dev->CIS.regs.channel == 0x40 ? "GREEN" :
402 (dev->CIS.regs.channel == 0xC0 ? "BLUE" : "unknown")))
429 Mustek_PP_1015_read_reg(Mustek_PP_CIS_dev * dev, Mustek_PP_1015R_reg reg)
434 SANEI_PA4S2_READBEGIN (dev->desc->fd, reg & 0x03);
435 SANEI_PA4S2_READBYTE (dev->desc->fd, &tmp);
436 SANEI_PA4S2_READEND (dev->desc->fd);
445 dev->CIS.regs.in_regs[reg & 0x03] = tmp;
458 Mustek_PP_1015_wait_bit(Mustek_PP_CIS_dev * dev, Mustek_PP_1015R_reg reg,
471 while (dev->desc->state != STATE_CANCELLED)
477 sanei_pa4s2_readbegin (dev->desc->fd, reg & 0x03);
478 sanei_pa4s2_readbyte (dev->desc->fd, &tmp);
479 sanei_pa4s2_readend (dev->desc->fd);
517 dev->CIS.regs.in_regs[reg & 0x03] = tmp;
519 return dev->desc->state != STATE_CANCELLED ? SANE_TRUE : SANE_FALSE;
553 Mustek_PP_1015_write_reg(Mustek_PP_CIS_dev * dev, Mustek_PP_1015W_reg reg, SANE_Byte val)
562 SANEI_PA4S2_WRITEBYTE (dev->desc->fd, 6, (1 << (4+regNo))+ regBank);
563 SANEI_PA4S2_WRITEBYTE (dev->desc->fd, 5, val);
564 SANEI_PA4S2_WRITEBYTE (dev->desc->fd, 6, regBank);
567 dev->CIS.regs.out_regs[regBank][regNo] = val;
587 Mustek_PP_1015_write_reg2(Mustek_PP_CIS_dev * dev, Mustek_PP_1015W_reg reg,
596 SANEI_PA4S2_WRITEBYTE (dev->desc->fd, 6, (1 << (4+regNo))+ regBank);
597 SANEI_PA4S2_WRITEBYTE (dev->desc->fd, 5, val1);
598 SANEI_PA4S2_WRITEBYTE (dev->desc->fd, 6, (1 << (5+regNo))+ regBank);
599 SANEI_PA4S2_WRITEBYTE (dev->desc->fd, 5, val2);
600 SANEI_PA4S2_WRITEBYTE (dev->desc->fd, 6, regBank);
603 dev->CIS.regs.out_regs[regBank][regNo] = val1;
604 dev->CIS.regs.out_regs[regBank][regNo+1] = val2;
625 Mustek_PP_1015_write_reg3(Mustek_PP_CIS_dev * dev, Mustek_PP_1015W_reg reg,
634 SANEI_PA4S2_WRITEBYTE (dev->desc->fd, 6, (1 << (4+regNo))+ regBank);
635 SANEI_PA4S2_WRITEBYTE (dev->desc->fd, 5, val1);
636 SANEI_PA4S2_WRITEBYTE (dev->desc->fd, 6, (1 << (5+regNo))+ regBank);
637 SANEI_PA4S2_WRITEBYTE (dev->desc->fd, 5, val2);
638 SANEI_PA4S2_WRITEBYTE (dev->desc->fd, 6, (1 << (6+regNo))+ regBank);
639 SANEI_PA4S2_WRITEBYTE (dev->desc->fd, 5, val3);
640 SANEI_PA4S2_WRITEBYTE (dev->desc->fd, 6, regBank);
643 dev->CIS.regs.out_regs[regBank][regNo ] = val1;
644 dev->CIS.regs.out_regs[regBank][regNo+1] = val2;
645 dev->CIS.regs.out_regs[regBank][regNo+2] = val3;
659 Mustek_PP_1015_write_reg_start(Mustek_PP_CIS_dev * dev, Mustek_PP_1015W_reg reg)
667 dev->CIS.regs.current_write_reg = reg;
670 dev->CIS.regs.write_count = 0;
673 SANEI_PA4S2_WRITEBYTE (dev->desc->fd, 6, (1 << (4+regNo))+ regBank);
680 Mustek_PP_1015_write_reg_val(Mustek_PP_CIS_dev * dev, SANE_Byte val)
683 SANE_Byte regBank = (dev->CIS.regs.current_write_reg & 0xF0) >> 4;
684 SANE_Byte regNo = (dev->CIS.regs.current_write_reg & 0x0F);
689 dev->CIS.regs.out_regs[regBank][regNo] = val;
692 SANEI_PA4S2_WRITEBYTE (dev->desc->fd, 5, val);
695 ++dev->CIS.regs.write_count;
703 Mustek_PP_1015_write_reg_stop(Mustek_PP_CIS_dev * dev)
705 SANE_Byte regBank = (dev->CIS.regs.current_write_reg & 0xF0) >> 4;
707 SANE_Byte regNo = (dev->CIS.regs.current_write_reg & 0x0F);
711 Mustek_PP_1015_reg_w_name(dev->CIS.regs.current_write_reg),
712 dev->CIS.regs.write_count);
717 SANEI_PA4S2_WRITEBYTE (dev->desc->fd, 6, regBank);
727 Mustek_PP_1015_send_command(Mustek_PP_CIS_dev * dev, SANE_Byte command)
730 SANEI_PA4S2_WRITEBYTE (dev->desc->fd, 6, command);
748 max2hw_hres(Mustek_PP_CIS_dev *dev, int dist)
750 return (int)((dist * dev->CIS.hw_hres) / dev->desc->dev->maxres + 0.5);
755 max2hw_vres(Mustek_PP_CIS_dev *dev, int dist)
757 return (int)((dist * dev->CIS.hw_vres) / dev->desc->dev->maxres + 0.5);
762 max2cis_hres(Mustek_PP_CIS_dev *dev, int dist)
764 return (int)((dist * dev->CIS.cisRes) / dev->desc->dev->maxres + 0.5);
768 cis2max_res(Mustek_PP_CIS_dev *dev, int dist)
770 return (int)((dist * dev->desc->dev->maxres) / dev->CIS.cisRes + 0.5);
775 hw2max_vres(Mustek_PP_CIS_dev *dev, int dist)
777 return (int)((dist * dev->desc->dev->maxres) / dev->CIS.hw_vres + 0.5);
785 cis_get_bank_count(Mustek_PP_CIS_dev *dev)
787 dev->bank_count = (Mustek_PP_1015_read_reg(dev, MA1015R_BANK_COUNT) & 0x7);
788 if (dev->CIS.use8KBank) dev->bank_count >>= 1;
795 cis_set_sti(Mustek_PP_CIS_dev *dev)
797 SANEI_PA4S2_WRITEBYTE(dev->desc->fd, 3, 0xFF);
798 dev->bank_count++;
799 dev->bank_count &= (dev->CIS.use8KBank == SANE_TRUE) ? 3 : 7;
806 cis_wait_bank_change (Mustek_PP_CIS_dev * dev, int bankcount)
823 cis_get_bank_count (dev);
830 while ((dev->bank_count != bankcount) && (diff < MUSTEK_PP_CIS_WAIT_BANK));
832 if (dev->bank_count != bankcount && dev->desc->state != STATE_CANCELLED)
835 tmp = Mustek_PP_1015_read_reg(dev, 3);
838 dev->bank_count, Mustek_PP_1015_show_val(tmp), bankcount,
842 return dev->bank_count == bankcount ? SANE_TRUE : SANE_FALSE;
859 cis_set_dpi_value (Mustek_PP_CIS_dev * dev)
863 if (dev->model == MUSTEK_PP_CIS1200PLUS)
866 switch (dev->CIS.hw_hres)
893 switch (dev->CIS.hw_hres)
918 Mustek_PP_1015_write_reg(dev, MA1015W_DPI_CONTROL, val | 0x04);
920 DBG (4, "cis_set_dpi_value: dpi: %d -> value 0x%02x\n", dev->CIS.hw_hres, val);
924 cis_set_ccd_channel (Mustek_PP_CIS_dev * dev)
930 assert (dev->CIS.channel < 3);
932 chancode = codes[dev->CIS.channel];
942 if (dev->CIS.setParameters)
944 chancode |= (dev->desc->mode == MODE_BW) ? 0x20: 0;
948 SANEI_PA4S2_WRITEBYTE (dev->desc->fd, 6, chancode);
951 dev->CIS.regs.channel = chancode;
956 cis_config_ccd (Mustek_PP_CIS_dev * dev)
960 if (dev->CIS.res != 0)
961 dev->CIS.hres_step =
962 SANE_FIX ((float) dev->CIS.hw_hres / (float) dev->CIS.res);
967 if (dev->CIS.cisRes == 600)
968 SANEI_PA4S2_WRITEBYTE (dev->desc->fd, 6, 0x96);
970 SANEI_PA4S2_WRITEBYTE (dev->desc->fd, 6, 0x86);
972 cis_set_dpi_value(dev);
974 if (dev->CIS.setParameters)
976 dev->CIS.channel = dev->desc->mode == MODE_COLOR ?
981 dev->CIS.channel = MUSTEK_PP_CIS_CHANNEL_GRAY;
984 cis_set_ccd_channel (dev);
986 Mustek_PP_1015_write_reg (dev, MA1015W_POWER_ON_DELAY, 0xAA);
987 Mustek_PP_1015_write_reg (dev, MA1015W_CCD_TIMING, 0x05);
988 Mustek_PP_1015_write_reg (dev, MA1015W_CCD_TIMING_ADJ, 0x00);
990 Mustek_PP_1015_send_command (dev, 0x45); /* or 0x05 for no 8kbank */
997 CIS_CLEAR_FULLFLAG(dev);
998 CIS_INC_READ(dev);
999 CIS_CLEAR_READ_BANK(dev);
1000 CIS_CLEAR_WRITE_ADDR(dev);
1001 CIS_CLEAR_WRITE_BANK(dev);
1002 CIS_CLEAR_TOGGLE(dev);
1031 if (dev->CIS.setParameters == SANE_TRUE)
1043 skipCount += max2cis_hres(dev, dev->CIS.skipimagebytes);
1045 dev->CIS.cisRes);
1046 skipCount += (int)(2.0/25.4*dev->CIS.cisRes);
1049 Mustek_PP_1015_write_reg (dev, MA1015W_SKIP_COUNT, skipCount / 32);
1054 Mustek_PP_1015_write_reg (dev, MA1015W_SKIP_COUNT, 0);
1059 skipCount = cis2max_res(dev, skipCount); /* Back to max res */
1061 Mustek_PP_1015_write_reg(dev, MA1015W_EXPOSE_TIME, dev->CIS.exposeTime);
1063 DBG(4, "cis_config_ccd: skipcount: %d imagebytes: %d\n", skipCount, dev->CIS.imagebytes);
1064 /* set_initial_skip_1015 (dev); */
1065 if (dev->CIS.setParameters == SANE_TRUE)
1067 Mustek_PP_1015_write_reg(dev, MA1015W_EXPOSE_TIME, dev->CIS.exposeTime);
1068 Mustek_PP_1015_write_reg(dev, MA1015W_POWER_ON_DELAY, 0xAA);
1070 Mustek_PP_1015_write_reg3(dev, MA1015W_RED_REF, 0x96, 0x96, 0x96);
1071 dev->CIS.adjustskip = max2hw_hres(dev, skipCount);
1072 byteCount = max2hw_hres(dev, skipCount + dev->CIS.imagebytes) + 2;
1073 dev->CIS.setParameters = SANE_FALSE;
1077 dev->CIS.adjustskip = 0;
1078 byteCount = max2hw_hres(dev, skipCount);
1081 dev->CIS.adjustskip, byteCount);
1083 Mustek_PP_1015_write_reg2(dev, MA1015W_BYTE_COUNT_HB,
1086 cis_get_bank_count (dev);
1091 cis_wait_motor_stable (Mustek_PP_CIS_dev * dev)
1095 Mustek_PP_1015_wait_bit (dev, MA1015R_MOTOR, MA1015B_MOTOR_STABLE,
1098 if (dev->engine_delay > 0)
1101 timeoutVal.tv_usec = dev->engine_delay*1000;
1109 cis_motor_forward (Mustek_PP_CIS_dev * dev)
1113 if (dev->model == MUSTEK_PP_CIS600)
1115 switch (dev->CIS.hw_vres)
1132 switch (dev->CIS.hw_vres)
1152 DBG(4, "cis_motor_forward: @%d dpi: 0x%02X.\n", dev->CIS.hw_vres, control);
1153 if (!cis_wait_motor_stable (dev))
1156 Mustek_PP_1015_write_reg(dev, MA1015W_MOTOR_CONTROL, control);
1160 cis_move_motor (Mustek_PP_CIS_dev * dev, SANE_Int steps) /* steps @ maxres */
1169 SANE_Byte savedExposeTime = dev->CIS.exposeTime;
1170 dev->CIS.exposeTime = 85;
1188 dev->CIS.exposeTime <<= 1;
1189 cis_config_ccd(dev);
1190 dev->CIS.exposeTime = savedExposeTime;
1204 if (dev->fast_skip) {
1212 M1015_DISPLAY_REGS(dev, "Before move");
1226 while (quadSteps-- > 0 && dev->desc->state != STATE_CANCELLED)
1228 cis_wait_motor_stable (dev);
1229 Mustek_PP_1015_write_reg(dev, MA1015W_MOTOR_CONTROL, quadStep);
1232 while (biSteps-- > 0 && dev->desc->state != STATE_CANCELLED)
1234 cis_wait_motor_stable (dev);
1235 Mustek_PP_1015_write_reg(dev, MA1015W_MOTOR_CONTROL, biStep);
1238 while (fullSteps-- > 0 && dev->desc->state != STATE_CANCELLED)
1240 cis_wait_motor_stable (dev);
1241 Mustek_PP_1015_write_reg(dev, MA1015W_MOTOR_CONTROL, fullStep);
1246 cis_set_et_pd_sti (Mustek_PP_CIS_dev * dev)
1248 Mustek_PP_1015_write_reg(dev, MA1015W_EXPOSE_TIME,
1249 dev->CIS.exposeTime);
1250 Mustek_PP_1015_write_reg(dev, MA1015W_POWER_ON_DELAY,
1251 dev->CIS.powerOnDelay[dev->CIS.channel]);
1252 cis_set_ccd_channel (dev);
1253 cis_set_sti (dev);
1261 cis_wait_next_channel (Mustek_PP_CIS_dev * dev)
1263 int moveAtChannel = dev->desc->mode == MODE_COLOR ?
1266 if (!cis_wait_bank_change (dev, dev->bank_count))
1272 moveAtChannel = (dev->desc->mode == MODE_COLOR) ?
1275 if (dev->CIS.channel == moveAtChannel && !dev->CIS.dontMove)
1277 cis_motor_forward (dev);
1280 cis_set_et_pd_sti (dev);
1282 if (dev->desc->mode == MODE_COLOR)
1284 ++dev->CIS.channel;
1285 dev->CIS.channel %= 3;
1296 cis_wait_read_ready (Mustek_PP_CIS_dev * dev)
1299 dev->CIS.dontIncRead = SANE_TRUE;
1301 dev->CIS.channel = dev->desc->mode == MODE_COLOR ?
1306 if (!cis_wait_next_channel(dev)) return SANE_FALSE;
1330 cis_read_line_low_level (Mustek_PP_CIS_dev * dev, SANE_Byte * buf,
1335 int ctr, skips = dev->CIS.adjustskip, cval;
1342 SANEI_PA4S2_READBEGIN (dev->desc->fd, 1);
1346 if (dev->CIS.delay) delay_read(dev->CIS.delay);
1347 SANEI_PA4S2_READBYTE (dev->desc->fd, &color);
1350 if (dev->CIS.hw_hres == dev->CIS.res)
1356 if (dev->CIS.delay) delay_read(dev->CIS.delay);
1357 SANEI_PA4S2_READBYTE (dev->desc->fd, &color);
1382 else if (dev->CIS.hw_hres > dev->CIS.res)
1391 if (dev->CIS.delay) delay_read(dev->CIS.delay);
1392 SANEI_PA4S2_READBYTE (dev->desc->fd, &color);
1402 pos += dev->CIS.hres_step;
1429 SANE_Int step = SANE_FIX(1) - dev->CIS.hres_step;
1435 if (dev->CIS.delay) delay_read(dev->CIS.delay);
1436 SANEI_PA4S2_READBYTE (dev->desc->fd, &color);
1448 if (++calctr >= dev->calib_pixels) {
1453 calctr = dev->calib_pixels - 1;
1491 SANEI_PA4S2_READEND (dev->desc->fd);
1496 cis_read_line (Mustek_PP_CIS_dev * dev, SANE_Byte* buf, SANE_Int pixel,
1499 if (!dev->CIS.dontIncRead)
1500 CIS_INC_READ(dev);
1502 dev->CIS.dontIncRead = SANE_FALSE;
1508 cis_read_line_low_level (dev, buf, pixel, NULL, NULL, NULL);
1513 cis_read_line_low_level (dev, buf, pixel,
1514 dev->calib_low[dev->CIS.channel],
1515 dev->calib_hi[dev->CIS.channel],
1516 (dev->desc->val[OPT_CUSTOM_GAMMA].w ?
1517 dev->desc->gamma_table[dev->CIS.channel] : NULL));
1520 return cis_wait_next_channel(dev);
1524 cis_get_next_line (Mustek_PP_CIS_dev * dev, SANE_Byte * buf)
1526 SANE_Byte *dest, *tmpbuf = dev->tmpbuf;
1527 int ctr, channel, first, last, stride, step = dev->CIS.line_step;
1530 if (dev->desc->mode == MODE_COLOR)
1546 dev->ccd_line++;
1547 if ((dev->line_diff >> SANE_FIXED_SCALE_SHIFT) != dev->ccd_line)
1549 cis_motor_forward (dev);
1553 dev->line_diff += step;
1557 if (!cis_read_line(dev, tmpbuf, dev->desc->params.pixels_per_line,
1562 for (ctr = 0; ctr < dev->desc->params.pixels_per_line; ctr++)
1570 while (!gotline && dev->desc->state != STATE_CANCELLED);
1574 cis_get_grayscale_line (Mustek_PP_CIS_dev * dev, SANE_Byte * buf)
1576 cis_get_next_line(dev, buf);
1580 cis_get_lineart_line (Mustek_PP_CIS_dev * dev, SANE_Byte * buf)
1585 cis_get_grayscale_line (dev, gbuf);
1586 memset (buf, 0xFF, dev->desc->params.bytes_per_line);
1588 for (ctr = 0; ctr < dev->desc->params.pixels_per_line; ctr++)
1589 buf[ctr >> 3] ^= ((gbuf[ctr] > dev->bw_limit) ? (1 << (7 - ctr % 8)) : 0);
1593 cis_get_color_line (Mustek_PP_CIS_dev * dev, SANE_Byte * buf)
1595 cis_get_next_line(dev, buf);
1603 cis_save_state (Mustek_PP_CIS_dev * dev)
1605 dev->Saved_CIS = dev->CIS;
1612 cis_restore_state (Mustek_PP_CIS_dev * dev)
1614 dev->CIS = dev->Saved_CIS;
1635 cis_maximize_dynamic_range(Mustek_PP_CIS_dev * dev)
1641 SANE_Int pixels = dev->calib_pixels;
1648 dev->CIS.powerOnDelay[channel] = 170;
1652 dev->CIS.setParameters = SANE_TRUE;
1653 dev->CIS.exposeTime = exposeTime[MUSTEK_PP_CIS_CHANNEL_GREEN];
1654 cis_config_ccd(dev);
1656 M1015_DISPLAY_REGS(dev, "before maximizing dynamic range");
1657 dev->CIS.dontMove = SANE_TRUE; /* Don't move while calibrating */
1659 if (!cis_wait_read_ready(dev) && dev->desc->state != STATE_CANCELLED)
1665 if (dev->desc->mode == MODE_COLOR)
1676 dev->CIS.channel = first;
1684 dev->CIS.powerOnDelay[channel] = (powerOnDelayLower[channel] +
1687 Mustek_PP_1015_write_reg(dev, MA1015W_POWER_ON_DELAY,
1688 dev->CIS.powerOnDelay[1]); /* Green */
1700 if (!cis_read_line(dev, &buf[channel][0], pixels,
1711 powerOnDelayLower[channel] = dev->CIS.powerOnDelay[channel];
1715 powerOnDelayUpper[channel] = dev->CIS.powerOnDelay[channel];
1723 dev->CIS.powerOnDelay[0], dev->CIS.powerOnDelay[1],
1724 dev->CIS.powerOnDelay[2]);
1726 dev->CIS.dontMove = SANE_FALSE;
1729 dev->CIS.powerOnDelay[0], dev->CIS.powerOnDelay[1],
1730 dev->CIS.powerOnDelay[2]);
1732 minExposeTime = (dev->CIS.hw_hres <= 300) ? 170 : 253;
1736 dev->CIS.powerOnDelay[channel] = (powerOnDelayLower[channel] +
1738 exposeTime[channel] -= dev->CIS.powerOnDelay[channel] - 1;
1739 dev->CIS.powerOnDelay[channel] = 1;
1743 dev->CIS.powerOnDelay[channel] +=
1749 dev->CIS.exposeTime = exposeTime[MUSTEK_PP_CIS_CHANNEL_GREEN];
1753 dev->CIS.powerOnDelay[0], dev->CIS.powerOnDelay[1],
1754 dev->CIS.powerOnDelay[2]);
1760 dev->CIS.exposeTime = 170;
1761 dev->CIS.powerOnDelay[0] = 120;
1762 dev->CIS.powerOnDelay[1] = 120;
1763 dev->CIS.powerOnDelay[2] = 120;
1769 cis_measure_extremes(Mustek_PP_CIS_dev * dev, SANE_Byte* calib[3],
1782 dev->CIS.channel = first;
1787 if (!cis_read_line(dev, &buf[channel%3][0], pixels,
1791 --dev->CIS.skipsToOrigin;
1799 if (!cis_read_line(dev, &buf[channel][0], pixels,
1811 --dev->CIS.skipsToOrigin;
1829 cis_normalize_ranges(Mustek_PP_CIS_dev * dev)
1833 SANE_Int pixels = dev->calib_pixels;
1836 if (dev->desc->mode == MODE_COLOR)
1849 if (!cis_measure_extremes(dev, dev->calib_hi, pixels, first, last)) {
1855 powerOnDelay[channel] = dev->CIS.powerOnDelay[channel];
1856 dev->CIS.powerOnDelay[channel] = dev->CIS.exposeTime;
1860 if (!cis_measure_extremes(dev, dev->calib_low, pixels, first, last)) {
1866 dev->CIS.powerOnDelay[channel] = powerOnDelay[channel];
1872 if (dev->calib_low[channel]) {
1873 cal_low = dev->calib_low[channel][p];
1877 if (dev->calib_hi[channel]) {
1878 cal_hi = dev->calib_hi[channel][p];
1885 dev->calib_hi[channel][p] = cal_low+1;
1888 dev->calib_low[channel][p] = cal_hi-1;
1907 cis_measure_delay(Mustek_PP_CIS_dev * dev)
1914 CIS_CLEAR_FULLFLAG(dev);
1915 CIS_CLEAR_WRITE_ADDR(dev);
1916 CIS_CLEAR_WRITE_BANK(dev);
1917 CIS_INC_READ(dev);
1918 CIS_CLEAR_READ_BANK(dev);
1920 M1015_DISPLAY_REGS(dev, "Before delay measurement");
1921 assert(dev->CIS.adjustskip == 0);
1929 Mustek_PP_1015_write_reg_start(dev, MA1015W_SRAM_SOURCE_PC);
1932 Mustek_PP_1015_write_reg_val(dev, buf[0][i]);
1934 Mustek_PP_1015_write_reg_stop(dev);
1937 dev->CIS.delay = 0; /* Initialize to zero, measure next */
1939 saved_res = dev->CIS.res;
1940 dev->CIS.res = dev->CIS.hw_hres;
1951 for (d = 0; d < 75 /* 255 */ && dev->desc->state != STATE_CANCELLED; d += 5)
1953 dev->CIS.delay = d;
1960 CIS_INC_READ(dev);
1961 CIS_CLEAR_READ_BANK(dev);
1962 cis_read_line_low_level (dev, &buf[1][0], 2048, NULL, NULL, NULL);
1963 if (dev->desc->state == STATE_CANCELLED) return SANE_FALSE;
1970 CIS_INC_READ(dev);
1971 CIS_CLEAR_READ_BANK(dev);
1972 cis_read_line_low_level (dev, &buf[1][0], 2048, NULL, NULL, NULL);
1973 if (dev->desc->state == STATE_CANCELLED) return SANE_FALSE;
1985 DBG (3, "cis_measure_delay: delay %d\n", dev->CIS.delay);
1990 dev->CIS.res = saved_res;
2001 dev->CIS.delay = 0;
2004 DBG (3, "cis_measure_delay: delay %d\n", dev->CIS.delay);
2009 cis_motor_control (Mustek_PP_CIS_dev * dev, u_char control)
2011 cis_wait_motor_stable (dev);
2012 Mustek_PP_1015_write_reg(dev, MA1015W_MOTOR_CONTROL, control);
2016 cis_return_home (Mustek_PP_CIS_dev * dev, SANE_Bool nowait)
2018 SANE_Byte savedExposeTime = dev->CIS.exposeTime;
2021 dev->CIS.exposeTime = 170;
2022 cis_config_ccd(dev);
2023 dev->CIS.exposeTime = savedExposeTime;
2025 cis_motor_control (dev, 0xEB);
2028 Mustek_PP_1015_wait_bit(dev, MA1015R_MOTOR, MA1015B_MOTOR_HOME,
2038 cis_reset_device (Mustek_PP_CIS_dev * dev)
2041 dev->CIS.adjustskip = 0;
2042 dev->CIS.dontIncRead = SANE_TRUE;
2043 dev->CIS.dontMove = SANE_FALSE;
2045 cis_save_state(dev);
2047 dev->CIS.hw_hres = 300;
2048 dev->CIS.channel = MUSTEK_PP_CIS_CHANNEL_GREEN;
2049 dev->CIS.setParameters = SANE_FALSE;
2050 dev->CIS.exposeTime = 0xAA;
2052 cis_config_ccd (dev);
2054 cis_restore_state(dev);
2059 cis_calibrate (Mustek_PP_CIS_dev * dev)
2061 int i, saved_res = dev->CIS.res, saved_vres = dev->CIS.hw_vres;
2110 dev->desc->state = STATE_SCANNING;
2112 cis_reset_device (dev);
2113 cis_return_home (dev, SANE_FALSE); /* Wait till it's home */
2117 dev->CIS.hw_vres = dev->desc->dev->maxres;
2119 dev->CIS.skipsToOrigin = dev->top_skip; /*max2hw_vres(dev, dev->top_skip); */
2121 if (!cis_measure_delay(dev))
2124 cis_reset_device (dev);
2127 Mustek_PP_1015_write_reg_start(dev, MA1015W_MOTOR_CONTROL);
2130 if (dev->model == MUSTEK_PP_CIS600)
2132 Mustek_PP_1015_write_reg_val (dev, 0x73);
2136 Mustek_PP_1015_write_reg_val (dev, 0x7B);
2138 cis_wait_motor_stable (dev);
2140 Mustek_PP_1015_write_reg_stop(dev);
2145 if (dev->CIS.hw_hres < dev->CIS.res)
2146 dev->CIS.res = dev->CIS.hw_hres;
2148 if (!cis_maximize_dynamic_range(dev))
2151 if (!cis_normalize_ranges(dev))
2154 dev->CIS.res = saved_res;
2155 dev->CIS.hw_vres = saved_vres;
2158 /* dev->CIS.skipsToOrigin = hw2max_vres(dev, dev->CIS.skipsToOrigin); */
2162 dev->CIS.skipsToOrigin);
2163 cis_move_motor(dev, dev->CIS.skipsToOrigin);
2165 if (dev->calib_mode)
2171 cis_return_home (dev, SANE_FALSE); /* Wait till it's home */
2174 return dev->desc->state != STATE_CANCELLED ? SANE_TRUE : SANE_FALSE;
2369 Mustek_pp_Handle *dev = hndl;
2375 sanei_pa4s2_close (dev->fd);
2381 dev->lamp_on = 0;
2382 dev->priv = cisdev;
2384 cisdev->desc = dev;
2385 cisdev->model = dev->dev->info;
2412 Mustek_pp_Handle *dev = hndl;
2413 Mustek_PP_CIS_dev *cisdev = dev->priv;
2444 cisdev->top_skip += MM_TO_PIXEL(dvalue, dev->dev->maxres);
2517 Mustek_pp_Handle *dev = hndl;
2518 Mustek_PP_CIS_dev *cisdev = dev->priv;
2520 sanei_pa4s2_enable (dev->fd, SANE_TRUE);
2525 sanei_pa4s2_enable (dev->fd, SANE_FALSE);
2527 sanei_pa4s2_close (dev->fd);
2529 DBG (6, "cis_close: lamp_on: %d\n", (int)dev->lamp_on);
2539 Mustek_pp_Handle *dev = hndl;
2540 Mustek_PP_CIS_dev *cisdev = dev->priv;
2541 SANE_Int pixels = dev->params.pixels_per_line;
2552 cisdev->CIS.imagebytes = dev->bottomX - dev->topX;
2553 cisdev->CIS.skipimagebytes = dev->topX;
2555 cisdev->CIS.res = dev->res;
2557 DBG (3, "cis_drv_start: %d dpi\n", dev->res);
2559 if (dev->res <= 50 && cisdev->model != MUSTEK_PP_CIS1200PLUS)
2563 else if (dev->res <= 75 && cisdev->model == MUSTEK_PP_CIS1200PLUS)
2567 else if (dev->res <= 100)
2571 else if (dev->res <= 200)
2575 else if (dev->res <= 300)
2585 else if (dev->res <= 400)
2597 if (dev->res <= 150)
2601 else if (dev->res <= 300)
2612 if (dev->res <= 300)
2616 else if (dev->res <= 600)
2627 (cisdev->model == MUSTEK_PP_CIS1200 && dev->res <= 300))
2635 if (dev->res > cisdev->CIS.hw_hres)
2636 cisdev->calib_pixels = (pixels * cisdev->CIS.hw_hres) / dev->res;
2643 sanei_pa4s2_enable (dev->fd, SANE_TRUE);
2677 sanei_pa4s2_enable (dev->fd, SANE_FALSE);
2680 dev->priv = NULL;
2686 if (pixels > (dev->dev->maxhsize >> 1))
2687 pixels = (dev->dev->maxhsize >> 1);
2696 sanei_pa4s2_enable (dev->fd, SANE_FALSE);
2699 free(cisdev); dev->priv = NULL;
2707 if (dev->mode == MODE_COLOR)
2724 free(cisdev); dev->priv = NULL;
2725 sanei_pa4s2_enable (dev->fd, SANE_FALSE);
2742 free(cisdev); dev->priv = NULL;
2746 /* M1015_DISPLAY_REGS(dev, "after calibration"); */
2750 cis_move_motor (cisdev, dev->topY); /* Measured in max resolution */
2760 sanei_pa4s2_enable (dev->fd, SANE_FALSE);
2773 cisdev->lines_left = dev->params.lines;
2775 dev->state = STATE_SCANNING;
2787 Mustek_pp_Handle *dev = hndl;
2788 Mustek_PP_CIS_dev *cisdev = dev->priv;
2790 sanei_pa4s2_enable (dev->fd, SANE_TRUE);
2791 switch (dev->mode)
2805 sanei_pa4s2_enable (dev->fd, SANE_FALSE);
2813 Mustek_pp_Handle *dev = hndl;
2814 Mustek_PP_CIS_dev *cisdev = dev->priv;
2818 dev->state = STATE_CANCELLED;
2821 sanei_pa4s2_enable (dev->fd, SANE_TRUE);
2830 sanei_pa4s2_enable (dev->fd, SANE_FALSE);
2849 DBG (6, "cis_drv_stop: lamp_on: %d\n", (int)dev->lamp_on);