Lines Matching refs:ssp
24 #include "ssp-process.h"
25 #include "ssp-intel.h"
26 #include "ssp-internal.h"
27 #include "ssp-debug.h"
43 struct intel_ssp_params *ssp = (struct intel_ssp_params *)nhlt->ssp_params;
44 int di = ssp->ssp_count;;
45 struct ssp_intel_config_data_1_5 *blob15 = &ssp->ssp_blob_1_5[di][hwi];
46 struct ssp_intel_config_data *blob = &ssp->ssp_blob[di][hwi];
49 blob15->gateway_attributes = ssp->ssp_blob[di][hwi].gateway_attributes;
68 ssp->ssp_prm[di].mdivr[hwi].count = 1;
69 blob15->mdivrcnt = ssp->ssp_prm[di].mdivr[hwi].count;
70 ssp->ssp_prm[di].mdivr[hwi].mdivrs[0] = blob->mdivr;
74 ssp->ssp_blob_ext[di][hwi].size;
79 struct intel_ssp_params *ssp = (struct intel_ssp_params *)nhlt->ssp_params;
101 if (!ssp)
104 di = ssp->ssp_count;
107 ssp->ssp_blob[di][hwi].gateway_attributes = 0;
110 for (i = 0; i < ssp->ssp_prm[di].hw_cfg[hwi].tdm_slots; i++)
111 ssp->ssp_blob[di][hwi].ts_group[j] |= (i << (i * 4));
113 ssp->ssp_blob[di][hwi].ts_group[j] |= (0xF << (i * 4));
118 ssp->ssp_blob[di][hwi].ssc0 = SSCR0_PSP | SSCR0_RIM | SSCR0_TIM;
121 ssp->ssp_blob[di][hwi].ssc1 = SSCR1_TTE | SSCR1_TTELP | SSCR1_TRAIL | SSCR1_RSRE |
125 ssp->ssp_blob[di][hwi].ssc2 = SSCR2_SDFD | SSCR2_TURM1;
128 ssp->ssp_blob[di][hwi].ssc3 = 0;
131 ssp->ssp_blob[di][hwi].sspsp = 0;
134 ssp->ssp_blob[di][hwi].sspsp2 = 0x0;
137 ssp->ssp_blob[di][hwi].ssioc = SSIOC_SCOE;
140 ssp->ssp_blob[di][hwi].sscto = 0x0;
143 ssp->ssp_blob[di][hwi].sstsa = SSTSA_SSTSA(ssp->ssp_prm[di].hw_cfg[hwi].tx_slots);
146 ssp->ssp_blob[di][hwi].ssrsa = SSRSA_SSRSA(ssp->ssp_prm[di].hw_cfg[hwi].rx_slots);
148 switch (ssp->ssp_prm[di].hw_cfg[hwi].format & SSP_FMT_CLOCK_PROVIDER_MASK) {
150 ssp->ssp_blob[di][hwi].ssc1 |= SSCR1_SCLKDIR | SSCR1_SFRMDIR;
153 ssp->ssp_blob[di][hwi].ssc1 |= SSCR1_SCFR;
157 ssp->ssp_blob[di][hwi].ssc1 |= SSCR1_SCLKDIR;
163 ssp->ssp_blob[di][hwi].ssc1 |= SSCR1_SCFR | SSCR1_SFRMDIR;
172 switch (ssp->ssp_prm[di].hw_cfg[hwi].format & SSP_FMT_INV_MASK) {
191 if (ssp->ssp_prm[di].clks_control &
194 ssp->ssp_blob[di][hwi].sspsp |= SSPSP_SCMODE((inverted_bclk ^ 0x3) & 0x3);
197 ssp->ssp_blob[di][hwi].sspsp |= SSPSP_SCMODE(inverted_bclk);
200 ssp->ssp_blob[di][hwi].ssc0 |= SSCR0_MOD | SSCR0_ACS;
205 ssp->ssp_blob[di][hwi].ssc1 |= (ssp->ssp_prm[di].quirks & SSP_INTEL_QUIRK_TINTE) ?
209 ssp->ssp_blob[di][hwi].ssc1 |= (ssp->ssp_prm[di].quirks & SSP_INTEL_QUIRK_PINTE) ?
215 ssp->ssp_blob[di][hwi].ssc1 |= (ssp->ssp_prm[di].quirks & SSP_INTEL_QUIRK_LBM) ?
221 ssp->ssp_blob[di][hwi].ssc2 |= (ssp->ssp_prm[di].quirks & SSP_INTEL_QUIRK_SMTATF) ?
227 ssp->ssp_blob[di][hwi].ssc2 |= (ssp->ssp_prm[di].quirks & SSP_INTEL_QUIRK_MMRATF) ?
233 ssp->ssp_blob[di][hwi].ssc2 |= (ssp->ssp_prm[di].quirks & SSP_INTEL_QUIRK_PSPSTWFDFD) ?
239 ssp->ssp_blob[di][hwi].ssc2 |= (ssp->ssp_prm[di].quirks & SSP_INTEL_QUIRK_PSPSRWFDFD) ?
242 if (!ssp->ssp_prm[di].hw_cfg[hwi].mclk_rate) {
244 ssp->ssp_prm[di].hw_cfg[hwi].mclk_rate);
248 if (!ssp->ssp_prm[di].hw_cfg[hwi].bclk_rate ||
249 ssp->ssp_prm[di].hw_cfg[hwi].bclk_rate > ssp->ssp_prm[di].hw_cfg[hwi].mclk_rate) {
251 ssp->ssp_prm[di].hw_cfg[hwi].bclk_rate,
252 ssp->ssp_prm[di].hw_cfg[hwi].mclk_rate);
257 if (ssp->ssp_prm[di].hw_cfg[hwi].bclk_rate % ssp->ssp_prm[di].hw_cfg[hwi].fsync_rate) {
259 ssp->ssp_prm[di].hw_cfg[hwi].bclk_rate,
260 ssp->ssp_prm[di].hw_cfg[hwi].fsync_rate);
265 bdiv = ssp->ssp_prm[di].hw_cfg[hwi].bclk_rate / ssp->ssp_prm[di].hw_cfg[hwi].fsync_rate;
266 if (bdiv < ssp->ssp_prm[di].hw_cfg[hwi].tdm_slot_width *
267 ssp->ssp_prm[di].hw_cfg[hwi].tdm_slots) {
269 ssp->ssp_prm[di].hw_cfg[hwi].tdm_slot_width *
270 ssp->ssp_prm[di].hw_cfg[hwi].tdm_slots);
275 if (ssp->ssp_prm[di].hw_cfg[hwi].tdm_slot_width > 38) {
277 ssp->ssp_prm[di].hw_cfg[hwi].tdm_slot_width);
281 bdiv_min = ssp->ssp_prm[di].hw_cfg[hwi].tdm_slots *
282 (ssp->ssp_prm[di].tdm_per_slot_padding_flag ?
283 ssp->ssp_prm[di].hw_cfg[hwi].tdm_slot_width :
284 ssp->ssp_prm[di].sample_valid_bits);
299 switch (ssp->ssp_prm[di].hw_cfg[hwi].format & SSP_FMT_FORMAT_MASK) {
304 ssp->ssp_blob[di][hwi].ssc0 |= SSCR0_FRDC(ssp->ssp_prm[di].hw_cfg[hwi].tdm_slots);
321 ssp->ssp_blob[di][hwi].sspsp |= SSPSP_SFRMP(inverted_frame);
342 ssp->ssp_blob[di][hwi].sspsp |= SSPSP_DMYSTOP(slot_end_padding);
344 ssp->ssp_blob[di][hwi].sspsp |= SSPSP_EDMYSTOP(slot_end_padding);
352 ssp->ssp_blob[di][hwi].ssc0 |= SSCR0_FRDC(ssp->ssp_prm[di].hw_cfg[hwi].tdm_slots);
355 ssp->ssp_blob[di][hwi].ssc2 &= ~SSCR2_LJDFD;
372 ssp->ssp_blob[di][hwi].sspsp |= SSPSP_SFRMP(!inverted_frame ? 1 : 0);
393 ssp->ssp_blob[di][hwi].sspsp |= SSPSP_DMYSTOP(slot_end_padding);
395 ssp->ssp_blob[di][hwi].sspsp |= SSPSP_EDMYSTOP(slot_end_padding);
408 ssp->ssp_blob[di][hwi].ssc0 |= SSCR0_MOD |
409 SSCR0_FRDC(ssp->ssp_prm[di].hw_cfg[hwi].tdm_slots);
414 if (cfs && ssp->ssp_prm[di].frame_pulse_width > 0 &&
415 ssp->ssp_prm[di].frame_pulse_width <=
417 frame_len = ssp->ssp_prm[di].frame_pulse_width;
421 if (ssp->ssp_prm[di].frame_pulse_width >
433 ssp->ssp_blob[di][hwi].sspsp |= SSPSP_SFRMP(!inverted_frame ? 1 : 0);
435 active_tx_slots = popcount(ssp->ssp_prm[di].hw_cfg[hwi].tx_slots);
436 active_rx_slots = popcount(ssp->ssp_prm[di].hw_cfg[hwi].rx_slots);
443 if (ssp->ssp_prm[di].tdm_per_slot_padding_flag) {
444 frame_end_padding = bdiv - ssp->ssp_prm[di].hw_cfg[hwi].tdm_slots *
445 ssp->ssp_prm[di].hw_cfg[hwi].tdm_slot_width;
447 slot_end_padding = ssp->ssp_prm[di].hw_cfg[hwi].tdm_slot_width -
448 ssp->ssp_prm[di].sample_valid_bits;
457 ssp->ssp_blob[di][hwi].sspsp |= SSPSP_DMYSTOP(slot_end_padding);
459 ssp->ssp_blob[di][hwi].sspsp |= SSPSP_EDMYSTOP(slot_end_padding);
462 ssp->ssp_blob[di][hwi].sspsp2 |= (frame_end_padding & SSPSP2_FEP_MASK);
467 ssp->ssp_prm[di].hw_cfg[hwi].format);
472 ssp->ssp_blob[di][hwi].sspsp |= SSPSP_FSRT;
474 ssp->ssp_blob[di][hwi].sspsp |= SSPSP_SFRMWDTH(frame_len);
476 data_size = ssp->ssp_prm[di].sample_valid_bits;
479 ssp->ssp_blob[di][hwi].ssc0 |= (SSCR0_EDSS | SSCR0_DSIZE(data_size - 16));
481 ssp->ssp_blob[di][hwi].ssc0 |= SSCR0_DSIZE(data_size);
484 total_sample_size = ssp->ssp_prm[di].hw_cfg[hwi].tdm_slot_width *
485 ssp->ssp_prm[di].hw_cfg[hwi].tdm_slots;
486 while (ssp->ssp_prm[di].io_clk % ((total_sample_size + end_padding) *
487 ssp->ssp_prm[di].hw_cfg[hwi].fsync_rate)) {
496 clk_div = ssp->ssp_prm[di].io_clk / ((total_sample_size + end_padding) *
497 ssp->ssp_prm[di].hw_cfg[hwi].fsync_rate);
501 ssp->ssp_blob[di][hwi].ssc0 |= SSCR0_SCR(clk_div - 1);
504 switch (ssp->ssp_prm[di].sample_valid_bits) {
516 ssp->ssp_prm[di].sample_valid_bits);
525 ssp->ssp_blob[di][hwi].ssc3 |= SSCR3_TX(tft) | SSCR3_RX(rft);
528 if (ssp->ssp_prm[di].io_clk % ssp->ssp_prm[di].hw_cfg[hwi].mclk_rate) {
533 clk_div = ssp->ssp_prm[di].io_clk / ssp->ssp_prm[di].hw_cfg[hwi].mclk_rate;
539 ssp->ssp_blob[di][hwi].mdivr = clk_div;
541 ssp->ssp_blob[di][hwi].ssc0 |= SSCR0_ECS;
543 ssp->ssp_blob[di][hwi].mdivc |= BIT(ssp->ssp_prm[di].mclk_id);
545 ssp->ssp_blob[di][hwi].mdivc |= MCDSS(SSP_CLOCK_AUDIO_CARDINAL);
547 ssp->ssp_blob[di][hwi].mdivc |= MNDSS(SSP_CLOCK_AUDIO_CARDINAL);
556 struct intel_ssp_params *ssp;
582 ssp = (struct intel_ssp_params *)nhlt->ssp_params;
583 di = ssp->ssp_count;
584 enabled = ssp->ssp_prm[di].aux_cfg[hwi].enabled;
585 aux = &(ssp->ssp_prm[di].aux_cfg[hwi]);
586 aux_blob = ssp->ssp_blob_ext[di][hwi].aux_blob;
728 ssp->ssp_blob_ext[di][hwi].size = total_size;
737 struct intel_ssp_params *ssp = (struct intel_ssp_params *)nhlt->ssp_params;
740 if (!ssp)
744 for (i = 0; i < ssp->ssp_hw_config_count[ssp->ssp_count]; i++) {
753 ssp_print_internal(ssp);
754 ssp_print_calculated(ssp);
756 ssp->ssp_count++;
763 struct intel_ssp_params *ssp = (struct intel_ssp_params *)nhlt->ssp_params;
765 if (!ssp)
768 *dir = ssp->ssp_prm[dai_index].direction;
776 struct intel_ssp_params *ssp = (struct intel_ssp_params *)nhlt->ssp_params;
778 if (!ssp)
781 *virtualbus_id = ssp->ssp_dai_index[dai_index];
782 *formats_count = ssp->ssp_hw_config_count[dai_index];
783 if (ssp->ssp_prm[dai_index].quirks & SSP_INTEL_QUIRK_BT_SIDEBAND)
787 if (ssp->ssp_prm[dai_index].quirks & SSP_INTEL_QUIRK_RENDER_FEEDBACK) {
800 struct intel_ssp_params *ssp = (struct intel_ssp_params *)nhlt->ssp_params;
802 if (!ssp)
805 *channel_count = ssp->ssp_prm[dai_index].hw_cfg[hw_index].tdm_slots;
806 *sample_rate = ssp->ssp_prm[dai_index].hw_cfg[hw_index].fsync_rate;
807 *bits_per_sample = ssp->ssp_prm[dai_index].hw_cfg[hw_index].tdm_slot_width;
813 * Build ssp vendor blob from calculated parameters.
815 * Supposed to be called after all ssp DAIs are parsed from topology and the final nhlt blob is
821 struct intel_ssp_params *ssp = (struct intel_ssp_params *)nhlt->ssp_params;
823 if (!ssp)
827 if (ssp->ssp_prm[dai_index].version == SSP_BLOB_VER_1_5)
828 *size = ssp->ssp_blob_1_5[dai_index][hw_config_index].size;
832 ssp->ssp_blob_ext[dai_index][hw_config_index].size;
839 struct intel_ssp_params *ssp = (struct intel_ssp_params *)nhlt->ssp_params;
841 if (!ssp || !ssp->ssp_count)
844 return ssp->ssp_count;
851 struct intel_ssp_params *ssp = (struct intel_ssp_params *)nhlt->ssp_params;
854 if (!ssp)
858 if (ssp->ssp_prm[dai_index].version == SSP_BLOB_VER_1_5) {
860 clock_len = sizeof(uint32_t) * ssp->ssp_prm[dai_index].mdivr[hw_config_index].count;
862 memcpy(vendor_blob, &ssp->ssp_blob_1_5[dai_index][hw_config_index], basic_len);
865 &ssp->ssp_prm[dai_index].mdivr[hw_config_index].mdivrs[0], clock_len);
868 ssp->ssp_blob_ext[dai_index][hw_config_index].aux_blob,
869 ssp->ssp_blob_ext[dai_index][hw_config_index].size);
874 memcpy(vendor_blob, &ssp->ssp_blob[dai_index][hw_config_index], basic_len);
877 ssp->ssp_blob_ext[dai_index][hw_config_index].aux_blob,
878 ssp->ssp_blob_ext[dai_index][hw_config_index].size);
889 struct intel_ssp_params *ssp = (struct intel_ssp_params *)nhlt->ssp_params;
893 if (!ssp)
898 ssp->ssp_prm[ssp->ssp_count].direction = NHLT_ENDPOINT_DIRECTION_RENDER;
900 ssp->ssp_prm[ssp->ssp_count].direction = NHLT_ENDPOINT_DIRECTION_CAPTURE;
902 ssp->ssp_prm[ssp->ssp_count].direction =
907 ssp->ssp_dai_index[ssp->ssp_count] = dai_index;
908 ssp->ssp_prm[ssp->ssp_count].io_clk = io_clk;
909 ssp->ssp_prm[ssp->ssp_count].bclk_delay = bclk_delay;
910 ssp->ssp_prm[ssp->ssp_count].sample_valid_bits = sample_bits;
911 ssp->ssp_prm[ssp->ssp_count].mclk_id = mclk_id;
912 ssp->ssp_prm[ssp->ssp_count].clks_control = clks_control;
913 ssp->ssp_prm[ssp->ssp_count].frame_pulse_width = frame_pulse_width;
916 ssp->ssp_prm[ssp->ssp_count].version = SSP_BLOB_VER_1_5;
918 ssp->ssp_prm[ssp->ssp_count].tdm_per_slot_padding_flag = 1;
920 ssp->ssp_prm[ssp->ssp_count].tdm_per_slot_padding_flag = 0;
922 ssp->ssp_prm[ssp->ssp_count].quirks = 0;
933 ssp->ssp_prm[ssp->ssp_count].quirks |= SSP_INTEL_QUIRK_LBM;
935 ssp->ssp_prm[ssp->ssp_count].quirks |= SSP_INTEL_QUIRK_BT_SIDEBAND;
938 ssp->ssp_prm[ssp->ssp_count].quirks |= SSP_INTEL_QUIRK_RENDER_FEEDBACK;
951 /* reset hw config count for this ssp instance */
952 ssp->ssp_hw_config_count[ssp->ssp_count] = 0;
963 struct intel_ssp_params *ssp = (struct intel_ssp_params *)nhlt->ssp_params;
966 if (!ssp)
972 hwi = ssp->ssp_hw_config_count[ssp->ssp_count];
975 ssp->ssp_prm[ssp->ssp_count].hw_cfg[hwi].format = SSP_FMT_I2S;
977 ssp->ssp_prm[ssp->ssp_count].hw_cfg[hwi].format = SSP_FMT_RIGHT_J;
979 ssp->ssp_prm[ssp->ssp_count].hw_cfg[hwi].format = SSP_FMT_LEFT_J;
981 ssp->ssp_prm[ssp->ssp_count].hw_cfg[hwi].format = SSP_FMT_DSP_A;
983 ssp->ssp_prm[ssp->ssp_count].hw_cfg[hwi].format = SSP_FMT_DSP_B;
985 fprintf(stderr, "no valid format specified for ssp: %s\n", format);
993 ssp->ssp_prm[ssp->ssp_count].hw_cfg[hwi].format |= SSP_FMT_CBP_CFP;
995 ssp->ssp_prm[ssp->ssp_count].hw_cfg[hwi].format |= SSP_FMT_CBP_CFC;
999 ssp->ssp_prm[ssp->ssp_count].hw_cfg[hwi].format |= SSP_FMT_CBC_CFP;
1001 ssp->ssp_prm[ssp->ssp_count].hw_cfg[hwi].format |= SSP_FMT_CBC_CFC;
1007 ssp->ssp_prm[ssp->ssp_count].hw_cfg[hwi].format |= SSP_FMT_IB_IF;
1009 ssp->ssp_prm[ssp->ssp_count].hw_cfg[hwi].format |= SSP_FMT_IB_NF;
1012 ssp->ssp_prm[ssp->ssp_count].hw_cfg[hwi].format |= SSP_FMT_NB_IF;
1014 ssp->ssp_prm[ssp->ssp_count].hw_cfg[hwi].format |= SSP_FMT_NB_NF;
1017 ssp->ssp_prm[ssp->ssp_count].hw_cfg[hwi].mclk_rate = mclk_freq;
1018 ssp->ssp_prm[ssp->ssp_count].hw_cfg[hwi].bclk_rate = bclk_freq;
1019 ssp->ssp_prm[ssp->ssp_count].hw_cfg[hwi].fsync_rate = fsync_freq;
1020 ssp->ssp_prm[ssp->ssp_count].hw_cfg[hwi].tdm_slots = tdm_slots;
1021 ssp->ssp_prm[ssp->ssp_count].hw_cfg[hwi].tdm_slot_width = tdm_slot_width;
1022 ssp->ssp_prm[ssp->ssp_count].hw_cfg[hwi].tx_slots = tx_slots;
1023 ssp->ssp_prm[ssp->ssp_count].hw_cfg[hwi].rx_slots = rx_slots;
1025 ssp->ssp_hw_config_count[ssp->ssp_count]++;
1032 struct intel_ssp_params *ssp = (struct intel_ssp_params *)nhlt->ssp_params;
1033 int di = ssp->ssp_count;
1034 int hwi = ssp->ssp_hw_config_count[di];
1039 ssp->ssp_prm[di].aux_cfg[hwi].enabled |= BIT(SSP_MN_DIVIDER_CONTROLS);
1041 ssp->ssp_prm[di].aux_cfg[hwi].mn.m_div = m_div;
1042 ssp->ssp_prm[di].aux_cfg[hwi].mn.n_div = n_div;
1050 struct intel_ssp_params *ssp = (struct intel_ssp_params *)nhlt->ssp_params;
1051 int di = ssp->ssp_count;
1052 int hwi = ssp->ssp_hw_config_count[di];
1057 ssp->ssp_prm[di].aux_cfg[hwi].enabled |= BIT(SSP_DMA_CLK_CONTROLS);
1059 ssp->ssp_prm[di].aux_cfg[hwi].clk.clock_warm_up = clock_warm_up;
1060 ssp->ssp_prm[di].aux_cfg[hwi].clk.mclk = mclk;
1061 ssp->ssp_prm[di].aux_cfg[hwi].clk.warm_up_ovr = warm_up_ovr;
1062 ssp->ssp_prm[di].aux_cfg[hwi].clk.clock_stop_delay = clock_stop_delay;
1063 ssp->ssp_prm[di].aux_cfg[hwi].clk.keep_running = keep_running;
1064 ssp->ssp_prm[di].aux_cfg[hwi].clk.clock_stop_ovr = clock_stop_ovr;
1074 struct intel_ssp_params *ssp;
1078 ssp = (struct intel_ssp_params *)nhlt->ssp_params;
1079 di = ssp->ssp_count;
1080 hwi = ssp->ssp_hw_config_count[di];
1083 tr = (struct ssp_aux_config_tr *)&(ssp->ssp_prm[di].aux_cfg[hwi].tr_start);
1085 ssp->ssp_prm[di].aux_cfg[hwi].enabled |= BIT(SSP_DMA_TRANSMISSION_START);
1104 struct intel_ssp_params *ssp;
1108 ssp = (struct intel_ssp_params *)nhlt->ssp_params;
1109 di = ssp->ssp_count;
1110 hwi = ssp->ssp_hw_config_count[di];
1113 tr = (struct ssp_aux_config_tr *)&(ssp->ssp_prm[di].aux_cfg[hwi].tr_stop);
1115 ssp->ssp_prm[di].aux_cfg[hwi].enabled |= BIT(SSP_DMA_TRANSMISSION_STOP);
1131 struct intel_ssp_params *ssp = (struct intel_ssp_params *)nhlt->ssp_params;
1132 int di = ssp->ssp_count;
1133 int hwi = ssp->ssp_hw_config_count[di];
1138 ssp->ssp_prm[di].aux_cfg[hwi].enabled |= BIT(SSP_DMA_ALWAYS_RUNNING_MODE);
1140 ssp->ssp_prm[di].aux_cfg[hwi].run.always_run = always_run;
1147 struct intel_ssp_params *ssp = (struct intel_ssp_params *)nhlt->ssp_params;
1148 int di = ssp->ssp_count;
1149 int hwi = ssp->ssp_hw_config_count[di];
1154 ssp->ssp_prm[di].aux_cfg[hwi].enabled |= BIT(SSP_DMA_SYNC_DATA);
1156 ssp->ssp_prm[di].aux_cfg[hwi].sync.sync_denominator = sync_denominator;
1163 struct intel_ssp_params *ssp = (struct intel_ssp_params *)nhlt->ssp_params;
1164 int di = ssp->ssp_count;
1165 int hwi = ssp->ssp_hw_config_count[di];
1171 count = ssp->ssp_prm[di].aux_cfg[hwi].sync.count;
1175 ssp->ssp_prm[di].aux_cfg[hwi].sync.nodes[count].node_id = node_id;
1176 ssp->ssp_prm[di].aux_cfg[hwi].sync.nodes[count].sampling_rate = sampling_rate;
1178 ssp->ssp_prm[di].aux_cfg[hwi].sync.count++;
1193 struct intel_ssp_params *ssp = (struct intel_ssp_params *)nhlt->ssp_params;
1194 int di = ssp->ssp_count;
1195 int hwi = ssp->ssp_hw_config_count[di];
1200 ssp->ssp_prm[di].aux_cfg[hwi].enabled |= BIT(SSP_DMA_CLK_CONTROLS_EXT);
1202 ssp->ssp_prm[di].aux_cfg[hwi].ext.mclk_policy_override = mclk_policy_override;
1203 ssp->ssp_prm[di].aux_cfg[hwi].ext.mclk_always_running = mclk_always_running;
1204 ssp->ssp_prm[di].aux_cfg[hwi].ext.mclk_starts_on_gtw_init = mclk_starts_on_gtw_init;
1205 ssp->ssp_prm[di].aux_cfg[hwi].ext.mclk_starts_on_run = mclk_starts_on_run;
1206 ssp->ssp_prm[di].aux_cfg[hwi].ext.mclk_starts_on_pause = mclk_starts_on_pause;
1207 ssp->ssp_prm[di].aux_cfg[hwi].ext.mclk_stops_on_pause = mclk_stops_on_pause;
1208 ssp->ssp_prm[di].aux_cfg[hwi].ext.mclk_stops_on_reset = mclk_stops_on_reset;
1209 ssp->ssp_prm[di].aux_cfg[hwi].ext.bclk_policy_override = bclk_policy_override;
1210 ssp->ssp_prm[di].aux_cfg[hwi].ext.bclk_always_running = bclk_always_running;
1211 ssp->ssp_prm[di].aux_cfg[hwi].ext.bclk_starts_on_gtw_init = bclk_starts_on_gtw_init;
1212 ssp->ssp_prm[di].aux_cfg[hwi].ext.bclk_starts_on_run = bclk_starts_on_run;
1213 ssp->ssp_prm[di].aux_cfg[hwi].ext.bclk_starts_on_pause = bclk_starts_on_pause;
1214 ssp->ssp_prm[di].aux_cfg[hwi].ext.bclk_stops_on_pause = bclk_stops_on_pause;
1215 ssp->ssp_prm[di].aux_cfg[hwi].ext.bclk_stops_on_reset = bclk_stops_on_reset;
1216 ssp->ssp_prm[di].aux_cfg[hwi].ext.sync_policy_override = sync_policy_override;
1217 ssp->ssp_prm[di].aux_cfg[hwi].ext.sync_always_running = sync_always_running;
1218 ssp->ssp_prm[di].aux_cfg[hwi].ext.sync_starts_on_gtw_init = sync_starts_on_gtw_init;
1219 ssp->ssp_prm[di].aux_cfg[hwi].ext.sync_starts_on_run = sync_starts_on_run;
1220 ssp->ssp_prm[di].aux_cfg[hwi].ext.sync_starts_on_pause = sync_starts_on_pause;
1221 ssp->ssp_prm[di].aux_cfg[hwi].ext.sync_stops_on_pause = sync_stops_on_pause;
1222 ssp->ssp_prm[di].aux_cfg[hwi].ext.sync_stops_on_reset = sync_stops_on_reset;
1229 struct intel_ssp_params *ssp = (struct intel_ssp_params *)nhlt->ssp_params;
1230 int di = ssp->ssp_count;
1231 int hwi = ssp->ssp_hw_config_count[di];
1236 ssp->ssp_prm[di].aux_cfg[hwi].enabled |= BIT(SSP_LINK_CLK_SOURCE);
1238 ssp->ssp_prm[di].aux_cfg[hwi].link.clock_source = clock_source;
1243 /* init ssp parameters, should be called before parsing dais */
1246 struct intel_ssp_params *ssp;
1249 ssp = calloc(1, sizeof(struct intel_ssp_params));
1250 if (!ssp)
1253 nhlt->ssp_params = ssp;
1254 ssp->ssp_count = 0;
1257 ssp->ssp_hw_config_count[i] = 0;
1259 ssp->ssp_prm[i].aux_cfg[j].sync.count = 0;