Lines Matching refs:clk
537 clk_div = 0xFFF; /* bypass clk divider */
560 struct ssp_intel_clk_ctl *clk;
604 clk = (struct ssp_intel_clk_ctl *)(aux_blob + aux_size);
608 clk->start |= SET_BITS(15, 0, aux->clk.clock_warm_up);
609 clk->start |= SET_BIT(16, aux->clk.mclk);
610 clk->start |= SET_BIT(17, aux->clk.warm_up_ovr);
611 clk->stop |= SET_BITS(15, 0, aux->clk.clock_stop_delay);
612 clk->stop |= SET_BIT(16, aux->clk.keep_running);
613 clk->stop |= SET_BIT(17, aux->clk.clock_stop_ovr);
1059 ssp->ssp_prm[di].aux_cfg[hwi].clk.clock_warm_up = clock_warm_up;
1060 ssp->ssp_prm[di].aux_cfg[hwi].clk.mclk = mclk;
1061 ssp->ssp_prm[di].aux_cfg[hwi].clk.warm_up_ovr = warm_up_ovr;
1062 ssp->ssp_prm[di].aux_cfg[hwi].clk.clock_stop_delay = clock_stop_delay;
1063 ssp->ssp_prm[di].aux_cfg[hwi].clk.keep_running = keep_running;
1064 ssp->ssp_prm[di].aux_cfg[hwi].clk.clock_stop_ovr = clock_stop_ovr;