Lines Matching refs:temp
248 uint32_t temp;
252 temp = XREAD4(sc, oper, XHCI_CRCR_LO);
253 if (temp & XHCI_CRCR_LO_CRR) {
255 temp &= ~(XHCI_CRCR_LO_CS | XHCI_CRCR_LO_CA);
264 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CS);
267 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CA);
274 temp = XREAD4(sc, oper, XHCI_CRCR_LO);
275 if (temp & XHCI_CRCR_LO_CRR) {
312 uint32_t temp;
328 temp = (XREAD4(sc, oper, XHCI_USBCMD) & XHCI_CMD_HCRST) |
330 if (!temp)
334 if (temp) {
346 temp = XREAD4(sc, oper, XHCI_USBSTS);
349 XWRITE4(sc, oper, XHCI_USBSTS, temp);
419 temp = XREAD4(sc, runt, XHCI_IMAN(0));
420 temp |= XHCI_IMAN_INTR_ENA;
421 XWRITE4(sc, runt, XHCI_IMAN(0), temp);
442 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
443 if (!temp)
446 if (temp) {
466 uint32_t temp;
481 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
482 if (temp)
486 if (!temp) {
496 uint32_t temp = 0;
506 temp = (XREAD4(sc, oper, XHCI_USBCMD) & XHCI_CMD_HCRST) |
508 if (!temp)
512 if (temp) {
523 uint32_t temp;
562 temp = XREAD4(sc, capa, XHCI_HCSPARAMS0);
564 DPRINTF("HCS0 = 0x%08x\n", temp);
567 if (XHCI_HCS0_CSZ(temp)) {
574 sc->sc_bus.dma_bits = (XHCI_HCS0_AC64(temp) &&
580 temp = XREAD4(sc, capa, XHCI_HCSPARAMS1);
583 sc->sc_noport = XHCI_HCS1_N_PORTS(temp);
591 sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp);
598 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
600 DPRINTF("HCS2=0x%08x\n", temp);
603 sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp);
614 sc->sc_erst_max = 1U << XHCI_HCS2_ERST_MAX(temp);
618 temp = XREAD4(sc, capa, XHCI_HCSPARAMS3);
621 sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) +
622 XHCI_HCS3_U2_DEL(temp) + 250 /* us */;
861 uint32_t temp;
872 temp = le32toh(trb->dwTrb2);
874 remainder = XHCI_TRB_2_REM_GET(temp);
875 status = XHCI_TRB_2_ERROR_GET(temp);
877 temp = le32toh(trb->dwTrb3);
878 epno = XHCI_TRB_3_EP_GET(temp);
879 index = XHCI_TRB_3_SLOT_GET(temp);
946 temp = le32toh(td->td_trb[i].dwTrb2);
947 remainder += XHCI_TRB_2_BYTES_GET(temp);
1042 uint32_t temp;
1063 temp = le32toh(phwr->hwr_events[i].dwTrb3);
1065 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0;
1070 event = XHCI_TRB_3_TYPE_GET(temp);
1130 uint32_t temp;
1162 temp = trb->dwTrb3;
1165 temp |= htole32(XHCI_TRB_3_CYCLE_BIT);
1167 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1169 temp &= ~htole32(XHCI_TRB_3_TC_BIT);
1171 phwr->hwr_commands[i].dwTrb3 = temp;
1184 temp = htole32(XHCI_TRB_3_TC_BIT |
1188 temp = htole32(XHCI_TRB_3_TC_BIT |
1192 phwr->hwr_commands[i].dwTrb3 = temp;
1228 temp = le32toh(trb->dwTrb3);
1235 if ((XHCI_TRB_3_TYPE_GET(temp) == XHCI_TRB_TYPE_ADDRESS_DEVICE) &&
1236 ((temp & XHCI_TRB_3_BSR_BIT) == 0)) {
1250 temp = le32toh(sc->sc_cmd_result[0]);
1251 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS) {
1252 if (!((XHCI_TRB_2_ERROR_GET(temp) == XHCI_TRB_ERROR_SLOT_NOT_ON) &&
1271 uint32_t temp;
1284 temp = le32toh(trb.dwTrb3);
1286 *pslot = XHCI_TRB_3_SLOT_GET(temp);
1296 uint32_t temp;
1302 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) |
1305 trb.dwTrb3 = htole32(temp);
1315 uint32_t temp;
1321 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) |
1325 temp |= XHCI_TRB_3_BSR_BIT;
1327 trb.dwTrb3 = htole32(temp);
1341 uint32_t temp;
1415 temp = le32toh(sc->sc_cmd_result[0]);
1417 (XHCI_TRB_2_ERROR_GET(temp) ==
1435 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3);
1436 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp);
1464 uint32_t temp;
1470 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) |
1474 temp |= XHCI_TRB_3_DCEP_BIT;
1476 trb.dwTrb3 = htole32(temp);
1486 uint32_t temp;
1492 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) |
1494 trb.dwTrb3 = htole32(temp);
1504 uint32_t temp;
1510 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) |
1515 temp |= XHCI_TRB_3_PRSV_BIT;
1517 trb.dwTrb3 = htole32(temp);
1527 uint32_t temp;
1533 temp = XHCI_TRB_2_STREAM_SET(stream_id);
1534 trb.dwTrb2 = htole32(temp);
1536 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) |
1539 trb.dwTrb3 = htole32(temp);
1549 uint32_t temp;
1555 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) |
1560 temp |= XHCI_TRB_3_SUSP_EP_BIT;
1562 trb.dwTrb3 = htole32(temp);
1571 uint32_t temp;
1577 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) |
1580 trb.dwTrb3 = htole32(temp);
1592 uint32_t temp;
1604 temp = XREAD4(sc, runt, XHCI_IMAN(0));
1607 if (temp & XHCI_IMAN_INTR_PEND)
1608 XWRITE4(sc, runt, XHCI_IMAN(0), temp);
1664 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp)
1682 shortpkt_old = temp->shortpkt;
1683 len_old = temp->len;
1689 td = temp->td;
1690 td_next = td_first = temp->td_next;
1693 if (temp->len == 0) {
1694 if (temp->shortpkt)
1699 temp->shortpkt = 1;
1703 average = temp->average;
1705 if (temp->len < average) {
1706 if (temp->len % temp->max_packet_size) {
1707 temp->shortpkt = 1;
1709 average = temp->len;
1726 temp->len -= average;
1738 temp->len -= average;
1744 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) {
1752 usbd_copy_out(temp->pc, temp->offset + buf_offset,
1789 usbd_get_page(temp->pc, temp->offset +
1804 npkt = (len_old - npkt_off + temp->max_packet_size - 1) /
1805 temp->max_packet_size;
1823 switch (temp->trb_type) {
1826 XHCI_TRB_3_TBC_SET(temp->tbc) |
1827 XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1830 } else if (temp->do_isoc_sync != 0) {
1831 temp->do_isoc_sync = 0;
1834 XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8);
1840 if (temp->direction == UE_DIR_IN)
1846 if (temp->direction == UE_DIR_IN)
1856 temp->trb_type = XHCI_TRB_TYPE_NORMAL;
1861 if (temp->direction == UE_DIR_IN)
1867 if (temp->direction == UE_DIR_IN)
1930 if (temp->last_frame) {
1938 temp->shortpkt = shortpkt_old;
1939 temp->len = len_old;
1947 if (temp->step_td != 0) {
1961 temp->td = td;
1962 temp->td_next = td_next;
1968 struct xhci_std_temp temp;
1974 temp.do_isoc_sync = 0;
1975 temp.step_td = 0;
1976 temp.tbc = 0;
1977 temp.tlbpc = 0;
1978 temp.average = xfer->max_hc_frame_size;
1979 temp.max_packet_size = xfer->max_packet_size;
1980 temp.sc = XHCI_BUS2SC(xfer->xroot->bus);
1981 temp.pc = NULL;
1982 temp.last_frame = 0;
1983 temp.offset = 0;
1984 temp.multishort = xfer->flags_int.isochronous_xfr ||
1994 temp.td = NULL;
1995 temp.td_next = td;
2018 x = XREAD4(temp.sc, runt, XHCI_MFINDEX);
2025 temp.isoc_delta = 8; /* 1ms */
2026 x += temp.isoc_delta - 1;
2027 x &= ~(temp.isoc_delta - 1);
2031 temp.isoc_delta = 1U << shift;
2032 x += temp.isoc_delta - 1;
2033 x &= ~(temp.isoc_delta - 1);
2053 temp.do_isoc_sync = 1;
2063 usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) +
2067 temp.isoc_frame = xfer->endpoint->isoc_next;
2068 temp.trb_type = XHCI_TRB_TYPE_ISOCH;
2076 temp.len = xfer->frlengths[0];
2077 temp.pc = xfer->frbuffers + 0;
2078 temp.shortpkt = temp.len ? 1 : 0;
2079 temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE;
2080 temp.direction = 0;
2086 temp.last_frame = 1;
2089 xhci_setup_generic_chain_sub(&temp);
2093 temp.isoc_delta = 0;
2094 temp.isoc_frame = 0;
2095 temp.trb_type = xfer->flags_int.control_did_data ?
2100 temp.isoc_delta = 0;
2101 temp.isoc_frame = 0;
2102 temp.trb_type = XHCI_TRB_TYPE_NORMAL;
2107 temp.pc = xfer->frbuffers + x;
2109 temp.direction = UE_GET_DIR(xfer->endpointno);
2115 temp.len = xfer->frlengths[x];
2116 temp.step_td = ((xfer->endpointno & UE_DIR_IN) &&
2117 x != 0 && temp.multishort == 0);
2125 temp.last_frame = 1;
2127 temp.last_frame = 1;
2130 if (temp.len == 0) {
2133 temp.shortpkt = 0;
2135 temp.tbc = 0;
2136 temp.tlbpc = mult - 1;
2146 temp.shortpkt = 1;
2150 if (temp.len > xfer->max_frame_size)
2151 temp.len = xfer->max_frame_size;
2154 tdpc = (temp.len + xfer->max_packet_size - 1) /
2157 temp.tbc = ((tdpc + mult - 1) / mult) - 1;
2158 temp.tlbpc = (tdpc % mult);
2160 if (temp.tlbpc == 0)
2161 temp.tlbpc = mult - 1;
2163 temp.tlbpc--;
2167 temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1;
2170 xhci_setup_generic_chain_sub(&temp);
2173 temp.offset += xfer->frlengths[x - 1];
2174 temp.isoc_frame += temp.isoc_delta;
2177 temp.pc = xfer->frbuffers + x;
2189 if (xhcictlstep || temp.sc->sc_ctlstep) {
2196 temp.step_td = (xfer->nframes != 0);
2198 temp.step_td = 0;
2200 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN;
2201 temp.len = 0;
2202 temp.pc = NULL;
2203 temp.shortpkt = 0;
2204 temp.last_frame = 1;
2205 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE;
2207 xhci_setup_generic_chain_sub(&temp);
2210 td = temp.td;
2242 uint32_t temp;
2283 temp = xhci_ctx_get_le32(sc, &pinp->ctx_slot.dwSctx0);
2284 temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31);
2285 temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1);
2286 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2303 uint32_t temp;
2340 temp = XHCI_EPCTX_0_EPSTATE_SET(0) |
2347 temp = XHCI_EPCTX_0_EPSTATE_SET(0) |
2368 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2371 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2377 temp |= XHCI_EPCTX_0_MULT_SET(mult - 1);
2388 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp);
2390 temp =
2402 temp |= XHCI_EPCTX_1_CERR_SET(3);
2406 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2409 temp |= XHCI_EPCTX_1_EPTYPE_SET(1);
2412 temp |= XHCI_EPCTX_1_EPTYPE_SET(2);
2415 temp |= XHCI_EPCTX_1_EPTYPE_SET(3);
2421 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2423 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp);
2429 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) |
2434 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8);
2437 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE);
2441 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp);
2464 uint64_t temp;
2470 temp = pepext->physaddr +
2476 XHCI_MAX_STREAMS) + x].qwTrb0 = htole64(temp);
2502 uint32_t temp;
2549 temp = XHCI_SCTX_0_ROUTE_SET(route) |
2555 temp |= XHCI_SCTX_0_SPEED_SET(2);
2560 temp |= XHCI_SCTX_0_MTT_SET(1);
2564 temp |= XHCI_SCTX_0_SPEED_SET(3);
2568 temp |= XHCI_SCTX_0_MTT_SET(1);
2572 temp |= XHCI_SCTX_0_SPEED_SET(1);
2577 temp |= XHCI_SCTX_0_MTT_SET(1);
2581 temp |= XHCI_SCTX_0_SPEED_SET(4);
2590 temp |= XHCI_SCTX_0_HUB_SET(1);
2592 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2594 temp = XHCI_SCTX_1_RH_PORT_SET(rh_port);
2597 temp |= XHCI_SCTX_1_NUM_PORTS_SET(
2607 temp |= XHCI_SCTX_1_MAX_EL_SET(sc->sc_exit_lat_max);
2618 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp);
2620 temp = XHCI_SCTX_2_IRQ_TARGET_SET(0);
2623 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET(
2634 temp |= XHCI_SCTX_2_TT_HUB_SID_SET(
2636 temp |= XHCI_SCTX_2_TT_PORT_NUM_SET(
2644 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp);
2650 temp = XHCI_SCTX_3_DEV_ADDR_SET(0) |
2653 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp);
3272 sc->sc_hub_desc.temp[0] = sc->sc_conf;
3323 sc->sc_hub_desc.temp,
3324 sizeof(sc->sc_hub_desc.temp),
3335 sc->sc_hub_desc.temp[0] = 0;
3479 (void)memset_s(sc->sc_hub_desc.temp, sizeof(sc->sc_hub_desc.temp), 0, len);
4005 uint8_t temp;
4019 err = xhci_cmd_enable_slot(sc, &temp);
4026 if (temp > sc->sc_noslot) {
4031 if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) {
4032 DPRINTF("slot %u already allocated.\n", temp);
4039 udev->controller_slot_id = temp;
4043 (void)memset_s(&sc->sc_hw.devs[temp], sizeof(sc->sc_hw.devs[0]), 0, sizeof(sc->sc_hw.devs[0]));
4047 sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED;