Lines Matching refs:sc
79 struct xhci_softc *sc;
117 static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val);
118 static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr);
119 static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val);
121 static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr);
137 xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep)
140 DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0));
141 DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1));
142 DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2));
143 DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4));
144 DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5));
145 DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6));
146 DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7));
150 xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl)
153 DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0));
154 DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1));
155 DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2));
156 DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3));
173 struct xhci_softc *sc = XHCI_BUS2SC(bus);
176 cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg,
179 cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg,
182 for (i = 0; i != sc->sc_noscratch; i++) {
183 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i],
189 xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val)
192 if (sc->sc_ctx_is_64_byte) {
202 xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr)
205 if (sc->sc_ctx_is_64_byte) {
215 xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val)
218 if (sc->sc_ctx_is_64_byte) {
229 xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr)
232 if (sc->sc_ctx_is_64_byte) {
243 xhci_reset_command_queue_locked(struct xhci_softc *sc)
252 temp = XREAD4(sc, oper, XHCI_CRCR_LO);
264 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CS);
265 XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
267 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CA);
268 XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
271 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 4);
274 temp = XREAD4(sc, oper, XHCI_CRCR_LO);
282 sc->sc_command_ccs = 1;
283 sc->sc_command_idx = 0;
285 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
297 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
299 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
300 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
306 xhci_start_controller(struct xhci_softc *sc)
318 sc->sc_event_ccs = 1;
319 sc->sc_event_idx = 0;
320 sc->sc_command_ccs = 1;
321 sc->sc_command_idx = 0;
324 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST);
328 temp = (XREAD4(sc, oper, XHCI_USBCMD) & XHCI_CMD_HCRST) |
329 (XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_CNR);
335 device_printf(sc->sc_bus.parent, "Controller "
342 XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot);
344 XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot);
346 temp = XREAD4(sc, oper, XHCI_USBSTS);
349 XWRITE4(sc, oper, XHCI_USBSTS, temp);
351 XWRITE4(sc, oper, XHCI_DNCTRL, 0);
354 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
368 for (i = 0; i != sc->sc_noscratch; i++) {
370 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp);
376 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
377 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
378 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
379 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
383 XREAD4(sc, runt, XHCI_ERSTSZ(0)), sc->sc_erst_max);
385 XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(sc->sc_erst_max));
388 XWRITE4(sc, runt, XHCI_IMOD(0), sc->sc_imod_default);
390 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
408 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
409 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
415 XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr);
416 XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32));
419 temp = XREAD4(sc, runt, XHCI_IMAN(0));
421 XWRITE4(sc, runt, XHCI_IMAN(0), temp);
429 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
430 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
434 usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc);
437 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS |
442 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
447 XWRITE4(sc, oper, XHCI_USBCMD, 0);
448 device_printf(sc->sc_bus.parent, "Run timeout.\n");
453 xhci_do_poll(&sc->sc_bus);
455 if (sc->sc_port_route != NULL) {
457 (void)sc->sc_port_route(sc->sc_bus.parent,
464 xhci_halt_controller(struct xhci_softc *sc)
471 sc->sc_capa_off = 0;
472 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
473 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF;
474 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
477 XWRITE4(sc, oper, XHCI_USBCMD, 0);
481 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
487 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n");
494 xhci_reset_controller(struct xhci_softc *sc)
502 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST);
506 temp = (XREAD4(sc, oper, XHCI_USBCMD) & XHCI_CMD_HCRST) |
507 (XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_CNR);
513 device_printf(sc->sc_bus.parent, "Controller "
521 xhci_init(struct xhci_softc *sc, device_t self, uint8_t dma32)
528 sc->sc_bus.parent = self;
531 sc->sc_bus.usbrev = USB_REV_3_0;
534 sc->sc_bus.methods = &xhci_bus_methods;
537 sc->sc_bus.devices = sc->sc_devices;
538 sc->sc_bus.devices_max = XHCI_MAX_DEVICES;
541 sc->sc_event_ccs = 1;
542 sc->sc_command_ccs = 1;
545 sc->sc_capa_off = 0;
546 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
547 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F;
548 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
550 DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off);
551 DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off);
552 DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off);
554 DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION));
556 if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) {
557 device_printf(sc->sc_bus.parent, "Controller does "
562 temp = XREAD4(sc, capa, XHCI_HCSPARAMS0);
568 sc->sc_ctx_is_64_byte = 1;
570 sc->sc_ctx_is_64_byte = 0;
574 sc->sc_bus.dma_bits = (XHCI_HCS0_AC64(temp) &&
578 sc->sc_ctx_is_64_byte ? 64 : 32, (int)sc->sc_bus.dma_bits);
580 temp = XREAD4(sc, capa, XHCI_HCSPARAMS1);
583 sc->sc_noport = XHCI_HCS1_N_PORTS(temp);
585 if (sc->sc_noport == 0) {
586 device_printf(sc->sc_bus.parent, "Invalid number "
587 "of ports: %u\n", sc->sc_noport);
591 sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp);
593 DPRINTF("Max slots: %u\n", sc->sc_noslot);
595 if (sc->sc_noslot > XHCI_MAX_DEVICES)
596 sc->sc_noslot = XHCI_MAX_DEVICES;
598 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
603 sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp);
605 if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) {
606 device_printf(sc->sc_bus.parent, "XHCI request "
611 DPRINTF("Max scratch: %u\n", sc->sc_noscratch);
614 sc->sc_erst_max = 1U << XHCI_HCS2_ERST_MAX(temp);
615 if (sc->sc_erst_max > XHCI_MAX_RSEG)
616 sc->sc_erst_max = XHCI_MAX_RSEG;
618 temp = XREAD4(sc, capa, XHCI_HCSPARAMS3);
621 sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) +
625 if (sc->sc_imod_default == 0)
626 sc->sc_imod_default = XHCI_IMOD_DEFAULT;
629 if (usb_bus_mem_alloc_all(&sc->sc_bus,
635 cv_init(&sc->sc_cmd_cv, "CMDQ");
636 sx_init(&sc->sc_cmd_sx, "CMDQ lock");
638 sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg;
639 sc->sc_config_msg[0].bus = &sc->sc_bus;
640 sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg;
641 sc->sc_config_msg[1].bus = &sc->sc_bus;
647 xhci_uninit(struct xhci_softc *sc)
655 usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc);
657 cv_destroy(&sc->sc_cmd_cv);
658 sx_destroy(&sc->sc_cmd_sx);
664 struct xhci_softc *sc = XHCI_BUS2SC(bus);
669 (void)xhci_halt_controller(sc);
670 (void)xhci_reset_controller(sc);
674 (void)xhci_halt_controller(sc);
675 (void)xhci_reset_controller(sc);
679 (void)xhci_start_controller(sc);
856 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb)
888 if (index > sc->sc_noslot) {
898 pepext = &sc->sc_hw.devs[index].endp[epno];
1024 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb)
1026 if (sc->sc_cmd_addr == trb->qwTrb0) {
1028 sc->sc_cmd_result[0] = trb->dwTrb2;
1029 sc->sc_cmd_result[1] = trb->dwTrb3;
1030 (void)cv_signal(&sc->sc_cmd_cv);
1037 xhci_interrupt_poll(struct xhci_softc *sc)
1050 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1056 usb_pc_cpu_invalidate(&sc->sc_hw.root_pc);
1058 i = sc->sc_event_idx;
1059 j = sc->sc_event_ccs;
1079 xhci_check_transfer(sc, &phwr->hwr_events[i]);
1082 retval |= xhci_check_command(sc, &phwr->hwr_events[i]);
1101 sc->sc_event_idx = i;
1102 sc->sc_event_ccs = j;
1117 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
1118 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
1124 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb,
1136 XHCI_CMD_ASSERT_LOCKED(sc);
1140 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1146 USB_BUS_LOCK(&sc->sc_bus);
1148 i = sc->sc_command_idx;
1149 j = sc->sc_command_ccs;
1160 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1173 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1178 sc->sc_cmd_addr = htole64(addr);
1194 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1200 sc->sc_command_idx = i;
1201 sc->sc_command_ccs = j;
1203 XWRITE4(sc, door, XHCI_DOORBELL(0), 0);
1205 err = (usb_error_t)cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx,
1212 if ((err != 0) && (xhci_interrupt_poll(sc) != 0)) {
1227 (xhci_reset_command_queue_locked(sc) == 0)) {
1244 usb_bus_reset_async_locked(&sc->sc_bus);
1250 temp = le32toh(sc->sc_cmd_result[0]);
1253 (XHCI_TRB_3_SLOT_GET(le32toh(sc->sc_cmd_result[1]))))) {
1258 trb->dwTrb2 = sc->sc_cmd_result[0];
1259 trb->dwTrb3 = sc->sc_cmd_result[1];
1262 USB_BUS_UNLOCK(&sc->sc_bus);
1268 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot)
1280 err = xhci_do_command(sc, &trb, XHCI_DO_CMD_TIMEOUT/* ms */);
1293 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id)
1307 return (xhci_do_command(sc, &trb, XHCI_DO_CMD_TIMEOUT/* ms */));
1311 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx,
1329 return (xhci_do_command(sc, &trb, XHCI_DO_CMD_TIMEOUT/* ms */));
1337 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
1352 hdev = &sc->sc_hw.devs[index];
1357 XHCI_CMD_LOCK(sc);
1411 err = xhci_cmd_set_address(sc, buf_inp.physaddr,
1415 temp = le32toh(sc->sc_cmd_result[0]);
1416 if ((address == 0) && (sc->sc_port_route != NULL) &&
1421 (void)sc->sc_port_route(sc->sc_bus.parent, 0, ~0);
1435 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3);
1451 XHCI_CMD_UNLOCK(sc);
1460 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx,
1478 return (xhci_do_command(sc, &trb, XHCI_DO_CMD_TIMEOUT/* ms */));
1482 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx,
1496 return (xhci_do_command(sc, &trb, XHCI_DO_CMD_TIMEOUT/* ms */));
1500 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve,
1519 return (xhci_do_command(sc, &trb, XHCI_DO_CMD_TIMEOUT/* ms */));
1523 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr,
1541 return (xhci_do_command(sc, &trb, XHCI_DO_CMD_TIMEOUT/* ms */));
1545 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend,
1564 return (xhci_do_command(sc, &trb, XHCI_DO_CMD_TIMEOUT/* ms */));
1568 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id)
1582 return (xhci_do_command(sc, &trb, XHCI_DO_CMD_TIMEOUT/* ms */));
1589 xhci_interrupt(unsigned int irq, struct xhci_softc *sc)
1594 USB_BUS_LOCK(&sc->sc_bus);
1596 status = XREAD4(sc, oper, XHCI_USBSTS);
1600 XWRITE4(sc, oper, XHCI_USBSTS, status);
1604 temp = XREAD4(sc, runt, XHCI_IMAN(0));
1608 XWRITE4(sc, runt, XHCI_IMAN(0), temp);
1611 (void)xhci_interrupt_poll(sc);
1616 xhci_root_intr(sc);
1634 USB_BUS_UNLOCK(&sc->sc_bus);
1656 struct xhci_softc *sc = XHCI_BUS2SC(bus);
1658 USB_BUS_LOCK(&sc->sc_bus);
1659 (void)xhci_interrupt_poll(sc);
1660 USB_BUS_UNLOCK(&sc->sc_bus);
1980 temp.sc = XHCI_BUS2SC(xfer->xroot->bus);
2018 x = XREAD4(temp.sc, runt, XHCI_MFINDEX);
2063 usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) +
2189 if (xhcictlstep || temp.sc->sc_ctlstep) {
2220 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr)
2225 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
2233 usb_pc_cpu_flush(&sc->sc_hw.ctx_pc);
2239 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2248 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2254 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask);
2255 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0);
2261 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0,
2265 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask);
2277 if (x > sc->sc_hw.devs[index].context_num)
2278 sc->sc_hw.devs[index].context_num = x;
2280 x = sc->sc_hw.devs[index].context_num;
2283 temp = xhci_ctx_get_le32(sc, &pinp->ctx_slot.dwSctx0);
2286 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2288 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc);
2300 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2310 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2388 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp);
2423 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp);
2424 xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr);
2441 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp);
2444 xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]);
2446 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc);
2497 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2513 pcinp = &sc->sc_hw.devs[index].input_pc;
2551 sc->sc_hw.devs[index].context_num + 1);
2565 if ((sc->sc_hw.devs[index].nports != 0) &&
2585 is_hub = sc->sc_hw.devs[index].nports != 0 &&
2592 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2598 sc->sc_hw.devs[index].nports);
2603 switch (sc->sc_hw.devs[index].state) {
2607 temp |= XHCI_SCTX_1_MAX_EL_SET(sc->sc_exit_lat_max);
2618 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp);
2624 sc->sc_hw.devs[index].tt);
2644 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp);
2653 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp);
2656 xhci_dump_device(sc, &pinp->ctx_slot);
2666 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2678 pc = &sc->sc_hw.devs[index].device_pc;
2679 pg = &sc->sc_hw.devs[index].device_pg;
2682 pc->tag_parent = sc->sc_bus.dma_parent_tag;
2684 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2691 pc = &sc->sc_hw.devs[index].input_pc;
2692 pg = &sc->sc_hw.devs[index].input_pg;
2695 pc->tag_parent = sc->sc_bus.dma_parent_tag;
2697 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2706 pc = &sc->sc_hw.devs[index].endpoint_pc[i];
2707 pg = &sc->sc_hw.devs[index].endpoint_pg[i];
2710 pc->tag_parent = sc->sc_bus.dma_parent_tag;
2736 xhci_set_slot_pointer(sc, index, buf_dev.physaddr);
2749 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2754 xhci_set_slot_pointer(sc, index, 0);
2756 usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc);
2757 usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc);
2759 usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc[i]);
2765 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2780 pc = &sc->sc_hw.devs[index].endpoint_pc[epno];
2784 pepext = &sc->sc_hw.devs[index].endp[epno];
2795 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2807 XWRITE4(sc, door, XHCI_DOORBELL(index),
2893 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2898 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus),
2899 &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
2977 xhci_root_intr(struct xhci_softc *sc)
2981 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2984 (void)memset_s(sc->sc_hub_idata, sizeof(sc->sc_hub_idata), 0, sizeof(sc->sc_hub_idata));
2986 for (i = 1; i <= sc->sc_noport; i++) {
2988 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & (
2993 sc->sc_hub_idata[i / 8] |= 1 << (i % 8);
2997 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
2998 sizeof(sc->sc_hub_idata));
3233 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3245 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3248 ptr = (const void *)&sc->sc_hub_desc;
3272 sc->sc_hub_desc.temp[0] = sc->sc_conf;
3310 str_ptr = sc->sc_vendor;
3323 sc->sc_hub_desc.temp,
3324 sizeof(sc->sc_hub_desc.temp),
3335 sc->sc_hub_desc.temp[0] = 0;
3339 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED);
3344 USETW(sc->sc_hub_desc.stat.wStatus, 0);
3357 sc->sc_conf = value;
3377 (index > sc->sc_noport)) {
3383 v = XREAD4(sc, oper, port);
3389 XWRITE4(sc, oper, port, v | XHCI_PS_WRC);
3392 XWRITE4(sc, oper, port, v | XHCI_PS_CEC);
3396 XWRITE4(sc, oper, port, v | XHCI_PS_PLC);
3399 XWRITE4(sc, oper, port, v | XHCI_PS_CSC);
3402 XWRITE4(sc, oper, port, v | XHCI_PS_PEC);
3405 XWRITE4(sc, oper, port, v | XHCI_PS_OCC);
3408 XWRITE4(sc, oper, port, v | XHCI_PS_PRC);
3411 XWRITE4(sc, oper, port, v | XHCI_PS_PED);
3414 XWRITE4(sc, oper, port, v & ~XHCI_PS_PP);
3417 XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3));
3423 XWRITE4(sc, oper, port, v |
3428 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
3431 XWRITE4(sc, oper, port, v |
3446 v = XREAD4(sc, capa, XHCI_HCSPARAMS0);
3448 sc->sc_hub_desc.hubd = xhci_hubd;
3450 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport;
3462 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i);
3465 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10;
3467 for (j = 1; j <= sc->sc_noport; j++) {
3468 v = XREAD4(sc, oper, XHCI_PORTSC(j));
3470 sc->sc_hub_desc.hubd.
3474 len = sc->sc_hub_desc.hubd.bLength;
3479 (void)memset_s(sc->sc_hub_desc.temp, sizeof(sc->sc_hub_desc.temp), 0, len);
3486 (index > sc->sc_noport)) {
3491 v = XREAD4(sc, oper, XHCI_PORTSC(index));
3527 USETW(sc->sc_hub_desc.ps.wPortStatus, i);
3545 USETW(sc->sc_hub_desc.ps.wPortChange, i);
3546 len = sizeof(sc->sc_hub_desc.ps);
3562 (index > sc->sc_noport)) {
3568 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR;
3577 v = XREAD4(sc, oper, port);
3580 XWRITE4(sc, oper, port, v);
3588 v = XREAD4(sc, oper, port);
3591 XWRITE4(sc, oper, port, v);
3594 XWRITE4(sc, oper, port, v | XHCI_PS_WPR);
3597 XWRITE4(sc, oper, port, v |
3600 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250);
3613 XWRITE4(sc, oper, port, v |
3618 XWRITE4(sc, oper, port, v | XHCI_PS_PR);
3622 XWRITE4(sc, oper, port, v | XHCI_PS_PP);
3633 XWRITE4(sc, oper, port, v);
3760 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3777 pcinp = &sc->sc_hw.devs[index].input_pc;
3794 XHCI_CMD_LOCK(sc);
3801 XHCI_CMD_UNLOCK(sc);
3810 err = xhci_cmd_stop_ep(sc, 0, epno, index);
3815 err = xhci_cmd_reset_ep(sc, 0, epno, index);
3820 err = xhci_cmd_set_tr_dequeue_ptr(sc,
3836 err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index);
3838 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
3843 XHCI_CMD_UNLOCK(sc);
3857 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3860 usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer);
3862 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus),
3863 &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
3869 struct xhci_softc *sc;
3873 sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus);
3876 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3909 USB_BUS_UNLOCK(&sc->sc_bus);
3913 USB_BUS_LOCK(&sc->sc_bus);
3936 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
4003 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4011 XHCI_CMD_LOCK(sc);
4015 udev->controller_slot_id = sc->sc_noslot + 1;
4019 err = xhci_cmd_enable_slot(sc, &temp);
4022 XHCI_CMD_UNLOCK(sc);
4026 if (temp > sc->sc_noslot) {
4027 XHCI_CMD_UNLOCK(sc);
4031 if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) {
4033 XHCI_CMD_UNLOCK(sc);
4043 (void)memset_s(&sc->sc_hw.devs[temp], sizeof(sc->sc_hw.devs[0]), 0, sizeof(sc->sc_hw.devs[0]));
4047 sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED;
4051 XHCI_CMD_UNLOCK(sc);
4064 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4071 XHCI_CMD_LOCK(sc);
4075 if (index <= sc->sc_noslot) {
4076 (void)xhci_cmd_disable_slot(sc, index);
4077 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED;
4083 XHCI_CMD_UNLOCK(sc);
4099 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4112 XHCI_CMD_LOCK(sc);
4120 XWRITE4(sc, door, XHCI_DOORBELL(index),
4127 XHCI_CMD_UNLOCK(sc);
4133 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4146 XHCI_CMD_LOCK(sc);
4151 err = xhci_cmd_stop_ep(sc, 1, n, index);
4158 XHCI_CMD_UNLOCK(sc);
4170 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4184 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports,
4185 &sc->sc_hw.devs[index].tt);
4187 sc->sc_hw.devs[index].nports = 0;
4190 XHCI_CMD_LOCK(sc);
4194 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT)
4198 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT;
4201 sc->sc_hw.devs[index].context_num = 0;
4203 err = xhci_cmd_reset_dev(sc, index);
4212 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED)
4215 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED;
4220 err = xhci_cmd_configure_ep(sc, 0, 1, index);
4229 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED)
4233 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED;
4236 sc->sc_hw.devs[index].context_num = 0;
4238 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
4248 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
4258 XHCI_CMD_UNLOCK(sc);