Lines Matching defs:index
868 uint8_t index;
879 index = XHCI_TRB_3_SLOT_GET(temp);
886 index, epno, remainder, status);
888 if (index > sc->sc_noslot) {
898 pepext = &sc->sc_hw.devs[index].endp[epno];
1344 uint8_t index;
1350 index = udev->controller_slot_id;
1352 hdev = &sc->sc_hw.devs[index];
1412 (address == 0), index);
1424 "for slot %u.\n", index);
1740 /* reset TRB index */
2220 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr)
2229 DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr);
2231 pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr);
2243 uint8_t index;
2246 index = udev->controller_slot_id;
2248 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2277 if (x > sc->sc_hw.devs[index].context_num)
2278 sc->sc_hw.devs[index].context_num = x;
2280 x = sc->sc_hw.devs[index].context_num;
2288 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc);
2304 uint8_t index;
2308 index = udev->controller_slot_id;
2310 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2446 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc);
2506 uint8_t index;
2509 index = udev->controller_slot_id;
2511 DPRINTF("index=%u\n", index);
2513 pcinp = &sc->sc_hw.devs[index].input_pc;
2551 sc->sc_hw.devs[index].context_num + 1);
2565 if ((sc->sc_hw.devs[index].nports != 0) &&
2585 is_hub = sc->sc_hw.devs[index].nports != 0 &&
2598 sc->sc_hw.devs[index].nports);
2603 switch (sc->sc_hw.devs[index].state) {
2624 sc->sc_hw.devs[index].tt);
2673 uint8_t index;
2676 index = udev->controller_slot_id;
2678 pc = &sc->sc_hw.devs[index].device_pc;
2679 pg = &sc->sc_hw.devs[index].device_pg;
2691 pc = &sc->sc_hw.devs[index].input_pc;
2692 pg = &sc->sc_hw.devs[index].input_pg;
2706 pc = &sc->sc_hw.devs[index].endpoint_pc[i];
2707 pg = &sc->sc_hw.devs[index].endpoint_pg[i];
2736 xhci_set_slot_pointer(sc, index, buf_dev.physaddr);
2750 uint8_t index;
2753 index = udev->controller_slot_id;
2754 xhci_set_slot_pointer(sc, index, 0);
2756 usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc);
2757 usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc);
2759 usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc[i]);
2770 uint8_t index;
2778 index = udev->controller_slot_id;
2780 pc = &sc->sc_hw.devs[index].endpoint_pc[epno];
2784 pepext = &sc->sc_hw.devs[index].endp[epno];
2797 uint8_t index;
2804 index = xfer->xroot->udev->controller_slot_id;
2807 XWRITE4(sc, door, XHCI_DOORBELL(index),
2905 /* get current TRB index */
2908 /* get next TRB index */
2915 /* store next TRB index, before stream ID offset is added */
3241 uint16_t index;
3253 index = UGETW(req->wIndex);
3258 UGETW(req->wLength), value, index);
3376 if ((index < 1) ||
3377 (index > sc->sc_noport)) {
3381 port = XHCI_PORTSC(index);
3483 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index);
3485 if ((index < 1) ||
3486 (index > sc->sc_noport)) {
3491 v = XREAD4(sc, oper, XHCI_PORTSC(index));
3558 i = index >> 8;
3559 index &= 0x00FF;
3561 if ((index < 1) ||
3562 (index > sc->sc_noport)) {
3567 port = XHCI_PORTSC(index);
3576 port = XHCI_PORTPMSC(index);
3587 port = XHCI_PORTPMSC(index);
3603 DPRINTFN(3, "set port enable %d\n", index);
3606 DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i);
3617 DPRINTFN(6, "reset port %d\n", index);
3621 DPRINTFN(3, "set port power %d\n", index);
3625 DPRINTFN(3, "set port test %d\n", index);
3628 DPRINTFN(3, "set port indicator %d\n", index);
3768 uint8_t index;
3775 index = udev->controller_slot_id;
3777 pcinp = &sc->sc_hw.devs[index].input_pc;
3810 err = xhci_cmd_stop_ep(sc, 0, epno, index);
3815 err = xhci_cmd_reset_ep(sc, 0, epno, index);
3823 stream_id, epno, index);
3836 err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index);
3838 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
4065 uint8_t index;
4073 index = udev->controller_slot_id;
4075 if (index <= sc->sc_noslot) {
4076 (void)xhci_cmd_disable_slot(sc, index);
4077 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED;
4100 uint8_t index;
4110 index = udev->controller_slot_id;
4120 XWRITE4(sc, door, XHCI_DOORBELL(index),
4134 uint8_t index;
4144 index = udev->controller_slot_id;
4151 err = xhci_cmd_stop_ep(sc, 1, n, index);
4154 "%u on slot %u (ignored).\n", n, index);
4173 uint8_t index;
4179 index = udev->controller_slot_id;
4184 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports,
4185 &sc->sc_hw.devs[index].tt);
4187 sc->sc_hw.devs[index].nports = 0;
4194 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT)
4198 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT;
4201 sc->sc_hw.devs[index].context_num = 0;
4203 err = xhci_cmd_reset_dev(sc, index);
4207 "for slot %u.\n", index);
4212 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED)
4215 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED;
4220 err = xhci_cmd_configure_ep(sc, 0, 1, index);
4224 "slot %u.\n", index);
4229 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED)
4233 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED;
4236 sc->sc_hw.devs[index].context_num = 0;
4238 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
4245 "at slot %u.\n", index);
4248 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
4251 "context at slot %u.\n", index);