Lines Matching defs:value
75 UINT32 value;
80 READ_UINT32(value, OS_TIMER_CLK_PWD_ADDR);
81 value &= ~(OS_TIMER_32K_CLK_BIT);
82 WRITE_UINT32(value, OS_TIMER_CLK_PWD_ADDR);
84 value = LOSCFG_BASE_CORE_TICK_RESPONSE_MAX;
85 WRITE_UINT32(value, OS_TIMER_PERIOD_REG_ADDR);
87 READ_UINT32(value, OS_TIMER_CTL_REG_ADDR);
88 value &= ~(OS_TIMER_CLKDIV_MASK << OS_TIMER_CLKDIV_POS); // The default is 1, and the clock does not divide.
89 value &= ~(OS_TIMER_INT_MASK << OS_TIMER_INT_POS); // Clearing interruption.
90 value |= 0x1 << OS_TIMER_INT_POS;
91 value |= OS_TIMER_ENABLE; // Enable timer.
92 WRITE_UINT32(value, OS_TIMER_CTL_REG_ADDR);
142 UINT32 value;
144 READ_UINT32(value, OS_TIMER_CTL_REG_ADDR);
145 value &= ~OS_TIMER_ENABLE;
146 value &= ~(OS_TIMER_INT_MASK << OS_TIMER_INT_POS);
147 value |= 0x1 << OS_TIMER_INT_POS;
148 WRITE_UINT32(value, OS_TIMER_CTL_REG_ADDR);
153 UINT32 value;
155 READ_UINT32(value, OS_TIMER_CTL_REG_ADDR);
156 value |= OS_TIMER_ENABLE;
157 value &= ~(OS_TIMER_INT_MASK << OS_TIMER_INT_POS);
158 value |= 0x1 << OS_TIMER_INT_POS;
159 WRITE_UINT32(value, OS_TIMER_CTL_REG_ADDR);