Lines Matching defs:items
2132 const struct intel_pt_blk_items *items,
2135 const u64 *gp_regs = items->val[INTEL_PT_GP_REGS_POS];
2136 u32 mask = items->mask[INTEL_PT_GP_REGS_POS];
2165 const struct intel_pt_blk_items *items,
2168 u32 mask = items->has_xmm & (regs_mask >> PERF_REG_X86_XMM0);
2169 const u64 *xmm = items->xmm;
2209 const struct intel_pt_blk_items *items)
2219 u32 mask = items->mask[i];
2220 const u64 *from = items->val[i];
2235 const struct intel_pt_blk_items *items = &ptq->state->items;
2255 if (items->has_ip)
2256 sample.ip = items->ip;
2257 else if (items->has_rip)
2258 sample.ip = items->rip;
2271 if (items->has_timestamp)
2272 timestamp = items->timestamp;
2288 (items->mask[INTEL_PT_GP_REGS_POS] ||
2289 items->mask[INTEL_PT_XMM_POS])) {
2293 sample.intr_regs.abi = items->is_32_bit ?
2298 pos = intel_pt_add_gp_regs(&sample.intr_regs, regs, items, regs_mask);
2300 intel_pt_add_xmm(&sample.intr_regs, pos, items, regs_mask);
2304 if (items->mask[INTEL_PT_LBR_0_POS] ||
2305 items->mask[INTEL_PT_LBR_1_POS] ||
2306 items->mask[INTEL_PT_LBR_2_POS]) {
2307 intel_pt_add_lbrs(ptq->last_branch, items);
2318 if (sample_type & PERF_SAMPLE_ADDR && items->has_mem_access_address)
2319 sample.addr = items->mem_access_address;
2326 if (items->has_mem_access_latency) {
2327 u64 weight = items->mem_access_latency >> 32;
2341 sample.ins_lat = items->mem_access_latency & 0xffff;
2343 sample.weight = items->mem_access_latency;
2345 if (!sample.weight && items->has_tsx_aux_info) {
2347 sample.weight = (u32)items->tsx_aux_info;
2351 if (sample_type & PERF_SAMPLE_TRANSACTION && items->has_tsx_aux_info) {
2352 u64 ax = items->has_rax ? items->rax : 0;
2354 u64 txn = (u8)(items->tsx_aux_info >> 32);
2376 const struct intel_pt_blk_items *items = &ptq->state->items;
2382 if (!items->has_applicable_counters || !items->applicable_counters) {
2388 for_each_set_bit(hw_id, (unsigned long *)&items->applicable_counters, INTEL_PT_MAX_PEBS) {