Lines Matching refs:regx
253 intelhaddata->aud_config.regx.aud_en = enable;
289 ch_stat0.regx.lpcm_id = (intelhaddata->aes_bits &
291 ch_stat0.regx.clk_acc = (intelhaddata->aes_bits &
296 ch_stat0.regx.samp_freq = CH_STATUS_MAP_32KHZ;
300 ch_stat0.regx.samp_freq = CH_STATUS_MAP_44KHZ;
303 ch_stat0.regx.samp_freq = CH_STATUS_MAP_48KHZ;
306 ch_stat0.regx.samp_freq = CH_STATUS_MAP_88KHZ;
309 ch_stat0.regx.samp_freq = CH_STATUS_MAP_96KHZ;
312 ch_stat0.regx.samp_freq = CH_STATUS_MAP_176KHZ;
315 ch_stat0.regx.samp_freq = CH_STATUS_MAP_192KHZ;
328 ch_stat1.regx.max_wrd_len = MAX_SMPL_WIDTH_20;
329 ch_stat1.regx.wrd_len = SMPL_WIDTH_16BITS;
333 ch_stat1.regx.max_wrd_len = MAX_SMPL_WIDTH_24;
334 ch_stat1.regx.wrd_len = SMPL_WIDTH_24BITS;
359 buf_cfg.regx.audio_fifo_watermark = FIFO_THRESHOLD;
360 buf_cfg.regx.dma_fifo_watermark = DMA_FIFO_THRESHOLD;
361 buf_cfg.regx.aud_delay = 0;
365 cfg_val.regx.num_ch = channels - 2;
367 cfg_val.regx.layout = LAYOUT0;
369 cfg_val.regx.layout = LAYOUT1;
372 cfg_val.regx.packet_mode = 1;
375 cfg_val.regx.left_align = 1;
377 cfg_val.regx.val_bit = 1;
381 cfg_val.regx.dp_modei = 1;
382 cfg_val.regx.set = 1;
613 frame2.regx.chnl_cnt = substream->runtime->channels - 1;
614 frame3.regx.chnl_alloc = ca;
624 frame2.regx.chksum = -(checksum);
635 ctrl_state.regx.dip_freq = 1;
636 ctrl_state.regx.dip_en_sta = 1;