Lines Matching defs:dbri
8 * Based entirely upon drivers/sbus/audio/dbri.c which is:
309 void __iomem *regs; /* dbri HW regs */
570 #define DBRI_STREAM(dbri, substream) \
571 &dbri->stream_info[DBRI_STREAMNO(substream)]
628 dbri->dma->cmd buffer. After this, the commands can be written to
638 static void dbri_cmdwait(struct snd_dbri *dbri)
644 spin_lock_irqsave(&dbri->lock, flags);
645 while ((--maxloops) > 0 && (sbus_readl(dbri->regs + REG0) & D_P)) {
646 spin_unlock_irqrestore(&dbri->lock, flags);
648 spin_lock_irqsave(&dbri->lock, flags);
650 spin_unlock_irqrestore(&dbri->lock, flags);
662 static s32 *dbri_cmdlock(struct snd_dbri *dbri, int len)
664 u32 dvma_addr = (u32)dbri->dma_dvma;
668 spin_lock(&dbri->cmdlock);
669 if (dbri->cmdptr - dbri->dma->cmd + len < DBRI_NO_CMDS - 2)
670 return dbri->cmdptr + 2;
671 else if (len < sbus_readl(dbri->regs + REG8) - dvma_addr)
672 return dbri->dma->cmd;
687 static void dbri_cmdsend(struct snd_dbri *dbri, s32 *cmd, int len)
689 u32 dvma_addr = (u32)dbri->dma_dvma;
699 addr = dvma_addr + (cmd - len - dbri->dma->cmd) * sizeof(s32);
700 *(dbri->cmdptr+1) = addr;
701 *(dbri->cmdptr) = DBRI_CMD(D_JUMP, 0, 0);
704 if (cmd > dbri->cmdptr) {
707 for (ptr = dbri->cmdptr; ptr < cmd+2; ptr++)
711 s32 *ptr = dbri->cmdptr;
716 for (ptr = dbri->dma->cmd; ptr < cmd+2; ptr++)
723 tmp = sbus_readl(dbri->regs + REG0);
725 sbus_writel(tmp, dbri->regs + REG0);
727 dbri->cmdptr = cmd;
728 spin_unlock(&dbri->cmdlock);
732 static void dbri_reset(struct snd_dbri *dbri)
738 sbus_readl(dbri->regs + REG0),
739 sbus_readl(dbri->regs + REG2),
740 sbus_readl(dbri->regs + REG8), sbus_readl(dbri->regs + REG9));
742 sbus_writel(D_R, dbri->regs + REG0); /* Soft Reset */
743 for (i = 0; (sbus_readl(dbri->regs + REG0) & D_R) && i < 64; i++)
748 tmp = sbus_readl(dbri->regs + REG0);
751 sbus_writel(tmp, dbri->regs + REG0);
755 static void dbri_initialize(struct snd_dbri *dbri)
757 u32 dvma_addr = (u32)dbri->dma_dvma;
763 spin_lock_irqsave(&dbri->lock, flags);
765 dbri_reset(dbri);
769 dbri->pipes[n].desc = dbri->pipes[n].first_desc = -1;
771 spin_lock_init(&dbri->cmdlock);
776 dbri->dma->intr[0] = dma_addr;
777 dbri->dbri_irqp = 1;
781 spin_lock(&dbri->cmdlock);
782 cmd = dbri->cmdptr = dbri->dma->cmd;
786 dbri->cmdptr = cmd;
790 sbus_writel(dma_addr, dbri->regs + REG8);
791 spin_unlock(&dbri->cmdlock);
793 spin_unlock_irqrestore(&dbri->lock, flags);
794 dbri_cmdwait(dbri);
811 static inline int pipe_active(struct snd_dbri *dbri, int pipe)
813 return ((pipe >= 0) && (dbri->pipes[pipe].desc != -1));
816 /* reset_pipe(dbri, pipe)
821 static void reset_pipe(struct snd_dbri *dbri, int pipe)
833 sdp = dbri->pipes[pipe].sdp;
840 cmd = dbri_cmdlock(dbri, 3);
844 dbri_cmdsend(dbri, cmd, 3);
846 desc = dbri->pipes[pipe].first_desc;
849 dbri->dma->desc[desc].ba = 0;
850 dbri->dma->desc[desc].nda = 0;
851 desc = dbri->next_desc[desc];
852 } while (desc != -1 && desc != dbri->pipes[pipe].first_desc);
854 dbri->pipes[pipe].desc = -1;
855 dbri->pipes[pipe].first_desc = -1;
861 static void setup_pipe(struct snd_dbri *dbri, int pipe, int sdp)
882 dbri->pipes[pipe].sdp = sdp;
883 dbri->pipes[pipe].desc = -1;
884 dbri->pipes[pipe].first_desc = -1;
886 reset_pipe(dbri, pipe);
892 static void link_time_slot(struct snd_dbri *dbri, int pipe,
907 if (dbri->pipes[pipe].sdp == 0
908 || dbri->pipes[prevpipe].sdp == 0
909 || dbri->pipes[nextpipe].sdp == 0) {
915 dbri->pipes[prevpipe].nextpipe = pipe;
916 dbri->pipes[pipe].nextpipe = nextpipe;
917 dbri->pipes[pipe].length = length;
919 cmd = dbri_cmdlock(dbri, 4);
921 if (dbri->pipes[pipe].sdp & D_SDP_TO_SER) {
928 cycle = dbri->chi_bpf;
944 dbri_cmdsend(dbri, cmd, 4);
951 static void unlink_time_slot(struct snd_dbri *dbri, int pipe,
966 cmd = dbri_cmdlock(dbri, 4);
981 dbri_cmdsend(dbri, cmd, 4);
1001 static void xmit_fixed(struct snd_dbri *dbri, int pipe, unsigned int data)
1011 if (D_SDP_MODE(dbri->pipes[pipe].sdp) == 0) {
1017 if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) {
1022 if (!(dbri->pipes[pipe].sdp & D_SDP_TO_SER)) {
1030 if (dbri->pipes[pipe].sdp & D_SDP_MSB)
1031 data = reverse_bytes(data, dbri->pipes[pipe].length);
1033 cmd = dbri_cmdlock(dbri, 3);
1039 spin_lock_irqsave(&dbri->lock, flags);
1040 dbri_cmdsend(dbri, cmd, 3);
1041 spin_unlock_irqrestore(&dbri->lock, flags);
1042 dbri_cmdwait(dbri);
1046 static void recv_fixed(struct snd_dbri *dbri, int pipe, volatile __u32 *ptr)
1054 if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) {
1060 if (dbri->pipes[pipe].sdp & D_SDP_TO_SER) {
1066 dbri->pipes[pipe].recv_fixed_ptr = ptr;
1085 static int setup_descs(struct snd_dbri *dbri, int streamno, unsigned int period)
1087 struct dbri_streaminfo *info = &dbri->stream_info[streamno];
1088 u32 dvma_addr = (u32)dbri->dma_dvma;
1100 if (dbri->pipes[info->pipe].sdp == 0) {
1110 if (!(dbri->pipes[info->pipe].sdp & D_SDP_TO_SER)) {
1116 if (dbri->pipes[info->pipe].sdp & D_SDP_TO_SER) {
1125 if (pipe_active(dbri, info->pipe)) {
1136 desc = dbri->pipes[info->pipe].first_desc;
1139 dbri->dma->desc[desc].ba = 0;
1140 dbri->dma->desc[desc].nda = 0;
1141 desc = dbri->next_desc[desc];
1143 desc != dbri->pipes[info->pipe].first_desc);
1145 dbri->pipes[info->pipe].desc = -1;
1146 dbri->pipes[info->pipe].first_desc = -1;
1153 if (!dbri->dma->desc[desc].ba)
1170 dbri->next_desc[desc] = -1;
1171 dbri->dma->desc[desc].ba = dvma_buffer;
1172 dbri->dma->desc[desc].nda = 0;
1175 dbri->dma->desc[desc].word1 = DBRI_TD_CNT(mylen);
1176 dbri->dma->desc[desc].word4 = 0;
1177 dbri->dma->desc[desc].word1 |= DBRI_TD_F | DBRI_TD_B;
1179 dbri->dma->desc[desc].word1 = 0;
1180 dbri->dma->desc[desc].word4 =
1187 dbri->next_desc[last_desc] = desc;
1188 dbri->dma->desc[last_desc].nda =
1203 dbri->dma->desc[last_desc].nda =
1205 dbri->next_desc[last_desc] = first_desc;
1206 dbri->pipes[info->pipe].first_desc = first_desc;
1207 dbri->pipes[info->pipe].desc = first_desc;
1213 dbri->dma->desc[desc].word1,
1214 dbri->dma->desc[desc].ba,
1215 dbri->dma->desc[desc].nda, dbri->dma->desc[desc].word4);
1216 desc = dbri->next_desc[desc];
1240 static void reset_chi(struct snd_dbri *dbri,
1249 cmd = dbri_cmdlock(dbri, 4);
1256 dbri_cmdsend(dbri, cmd, 4);
1258 dbri->pipes[16].sdp = 1;
1259 dbri->pipes[16].nextpipe = 16;
1261 cmd = dbri_cmdlock(dbri, 4);
1289 dbri->chi_bpf = bits_per_frame;
1303 dbri_cmdsend(dbri, cmd, 4);
1317 static void cs4215_setup_pipes(struct snd_dbri *dbri)
1321 spin_lock_irqsave(&dbri->lock, flags);
1337 setup_pipe(dbri, 4, D_SDP_MEM | D_SDP_TO_SER | D_SDP_MSB);
1338 setup_pipe(dbri, 20, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB);
1339 setup_pipe(dbri, 6, D_SDP_MEM | D_SDP_FROM_SER | D_SDP_MSB);
1340 setup_pipe(dbri, 21, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1342 setup_pipe(dbri, 17, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB);
1343 setup_pipe(dbri, 18, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1344 setup_pipe(dbri, 19, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1345 spin_unlock_irqrestore(&dbri->lock, flags);
1347 dbri_cmdwait(dbri);
1384 static void cs4215_setdata(struct snd_dbri *dbri, int muted)
1387 dbri->mm.data[0] |= 63;
1388 dbri->mm.data[1] |= 63;
1389 dbri->mm.data[2] &= ~15;
1390 dbri->mm.data[3] &= ~15;
1393 struct dbri_streaminfo *info = &dbri->stream_info[DBRI_PLAY];
1397 dbri->mm.data[0] &= ~0x3f; /* Reset the volume bits */
1398 dbri->mm.data[1] &= ~0x3f;
1399 dbri->mm.data[0] |= (DBRI_MAX_VOLUME - left_gain);
1400 dbri->mm.data[1] |= (DBRI_MAX_VOLUME - right_gain);
1403 info = &dbri->stream_info[DBRI_REC];
1406 dbri->mm.data[2] |= CS4215_LG(left_gain);
1407 dbri->mm.data[3] |= CS4215_RG(right_gain);
1410 xmit_fixed(dbri, 20, *(int *)dbri->mm.data);
1416 static void cs4215_open(struct snd_dbri *dbri)
1423 dbri->mm.channels, dbri->mm.precision);
1429 cs4215_setdata(dbri, 1);
1445 spin_lock_irqsave(&dbri->lock, flags);
1446 tmp = sbus_readl(dbri->regs + REG0);
1448 sbus_writel(tmp, dbri->regs + REG0);
1452 (dbri->mm.onboard ? D_PIO0 : D_PIO2), dbri->regs + REG2);
1454 reset_chi(dbri, CHIslave, 128);
1462 data_width = dbri->mm.channels * dbri->mm.precision;
1464 link_time_slot(dbri, 4, 16, 16, data_width, dbri->mm.offset);
1465 link_time_slot(dbri, 20, 4, 16, 32, dbri->mm.offset + 32);
1466 link_time_slot(dbri, 6, 16, 16, data_width, dbri->mm.offset);
1467 link_time_slot(dbri, 21, 6, 16, 16, dbri->mm.offset + 40);
1470 tmp = sbus_readl(dbri->regs + REG0);
1472 sbus_writel(tmp, dbri->regs + REG0);
1473 spin_unlock_irqrestore(&dbri->lock, flags);
1475 cs4215_setdata(dbri, 0);
1481 static int cs4215_setctrl(struct snd_dbri *dbri)
1492 cs4215_setdata(dbri, 1);
1499 val = D_ENPIO | D_PIO1 | (dbri->mm.onboard ? D_PIO0 : D_PIO2);
1500 sbus_writel(val, dbri->regs + REG2);
1522 spin_lock_irqsave(&dbri->lock, flags);
1523 tmp = sbus_readl(dbri->regs + REG0);
1525 sbus_writel(tmp, dbri->regs + REG0);
1527 reset_chi(dbri, CHImaster, 128);
1536 link_time_slot(dbri, 17, 16, 16, 32, dbri->mm.offset);
1537 link_time_slot(dbri, 18, 16, 16, 8, dbri->mm.offset);
1538 link_time_slot(dbri, 19, 18, 16, 8, dbri->mm.offset + 48);
1539 spin_unlock_irqrestore(&dbri->lock, flags);
1542 dbri->mm.ctrl[0] &= ~CS4215_CLB;
1543 xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl);
1545 spin_lock_irqsave(&dbri->lock, flags);
1546 tmp = sbus_readl(dbri->regs + REG0);
1548 sbus_writel(tmp, dbri->regs + REG0);
1549 spin_unlock_irqrestore(&dbri->lock, flags);
1551 for (i = 10; ((dbri->mm.status & 0xe4) != 0x20); --i)
1556 dbri->mm.status);
1563 recv_fixed(dbri, 19, NULL);
1568 dbri->mm.ctrl[0] |= CS4215_CLB;
1569 xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl);
1574 cs4215_setdata(dbri, 0);
1585 static int cs4215_prepare(struct snd_dbri *dbri, unsigned int rate,
1603 dbri->mm.ctrl[1] = CS4215_DFR_ULAW;
1604 dbri->mm.precision = 8;
1607 dbri->mm.ctrl[1] = CS4215_DFR_ALAW;
1608 dbri->mm.precision = 8;
1611 dbri->mm.ctrl[1] = CS4215_DFR_LINEAR8;
1612 dbri->mm.precision = 8;
1615 dbri->mm.ctrl[1] = CS4215_DFR_LINEAR16;
1616 dbri->mm.precision = 16;
1624 dbri->mm.ctrl[1] |= CS4215_FREQ[freq_idx].csval;
1625 dbri->mm.ctrl[2] = CS4215_XCLK |
1628 dbri->mm.channels = channels;
1630 dbri->mm.ctrl[1] |= CS4215_DFR_STEREO;
1632 ret = cs4215_setctrl(dbri);
1634 cs4215_open(dbri); /* set codec to data mode */
1642 static int cs4215_init(struct snd_dbri *dbri)
1644 u32 reg2 = sbus_readl(dbri->regs + REG2);
1650 dbri->mm.onboard = 1;
1654 dbri->mm.onboard = 0;
1659 sbus_writel(D_ENPIO2, dbri->regs + REG2);
1668 cs4215_setup_pipes(dbri);
1669 cs4215_init_data(&dbri->mm);
1672 recv_fixed(dbri, 18, &dbri->mm.status);
1673 recv_fixed(dbri, 19, &dbri->mm.version);
1675 dbri->mm.offset = dbri->mm.onboard ? 0 : 8;
1676 if (cs4215_setctrl(dbri) == -1 || dbri->mm.version == 0xff) {
1678 dbri->mm.offset);
1681 dprintk(D_MM, "Found CS4215 at offset %d\n", dbri->mm.offset);
1706 static void xmit_descs(struct snd_dbri *dbri)
1714 if (dbri == NULL)
1717 dvma_addr = (u32)dbri->dma_dvma;
1718 info = &dbri->stream_info[DBRI_REC];
1719 spin_lock_irqsave(&dbri->lock, flags);
1722 first_td = dbri->pipes[info->pipe].first_desc;
1728 cmd = dbri_cmdlock(dbri, 2);
1730 dbri->pipes[info->pipe].sdp
1734 dbri_cmdsend(dbri, cmd, 2);
1737 dbri->pipes[info->pipe].desc = first_td;
1741 info = &dbri->stream_info[DBRI_PLAY];
1744 first_td = dbri->pipes[info->pipe].first_desc;
1750 cmd = dbri_cmdlock(dbri, 2);
1752 dbri->pipes[info->pipe].sdp
1756 dbri_cmdsend(dbri, cmd, 2);
1759 dbri->pipes[info->pipe].desc = first_td;
1763 spin_unlock_irqrestore(&dbri->lock, flags);
1780 static void transmission_complete_intr(struct snd_dbri *dbri, int pipe)
1782 struct dbri_streaminfo *info = &dbri->stream_info[DBRI_PLAY];
1783 int td = dbri->pipes[pipe].desc;
1792 status = DBRI_TD_STATUS(dbri->dma->desc[td].word4);
1798 dbri->dma->desc[td].word4 = 0; /* Reset it for next time. */
1799 info->offset += DBRI_RD_CNT(dbri->dma->desc[td].word1);
1801 td = dbri->next_desc[td];
1802 dbri->pipes[pipe].desc = td;
1806 spin_unlock(&dbri->lock);
1808 spin_lock(&dbri->lock);
1811 static void reception_complete_intr(struct snd_dbri *dbri, int pipe)
1814 int rd = dbri->pipes[pipe].desc;
1822 dbri->pipes[pipe].desc = dbri->next_desc[rd];
1823 status = dbri->dma->desc[rd].word1;
1824 dbri->dma->desc[rd].word1 = 0; /* Reset it for next time. */
1826 info = &dbri->stream_info[DBRI_REC];
1835 spin_unlock(&dbri->lock);
1837 spin_lock(&dbri->lock);
1840 static void dbri_process_one_interrupt(struct snd_dbri *dbri, int x)
1864 reception_complete_intr(dbri, channel);
1868 transmission_complete_intr(dbri, channel);
1880 int td = dbri->pipes[pipe].desc;
1882 dbri->dma->desc[td].word4 = 0;
1883 cmd = dbri_cmdlock(dbri, NoGetLock);
1885 dbri->pipes[pipe].sdp
1887 *(cmd++) = dbri->dma_dvma + dbri_dma_off(desc, td);
1888 dbri_cmdsend(dbri, cmd);
1894 if (dbri->pipes[channel].sdp & D_SDP_MSB)
1895 val = reverse_bytes(val, dbri->pipes[channel].length);
1897 if (dbri->pipes[channel].recv_fixed_ptr)
1898 *(dbri->pipes[channel].recv_fixed_ptr) = val;
1912 static void dbri_process_interrupt_buffer(struct snd_dbri *dbri)
1916 while ((x = dbri->dma->intr[dbri->dbri_irqp]) != 0) {
1917 dbri->dma->intr[dbri->dbri_irqp] = 0;
1918 dbri->dbri_irqp++;
1919 if (dbri->dbri_irqp == DBRI_INT_BLK)
1920 dbri->dbri_irqp = 1;
1922 dbri_process_one_interrupt(dbri, x);
1928 struct snd_dbri *dbri = dev_id;
1932 if (dbri == NULL)
1934 spin_lock(&dbri->lock);
1939 x = sbus_readl(dbri->regs + REG1);
1969 dbri_reset(dbri);
1971 tmp = sbus_readl(dbri->regs + REG0);
1973 sbus_writel(tmp, dbri->regs + REG0);
1977 dbri_process_interrupt_buffer(dbri);
1979 spin_unlock(&dbri->lock);
2045 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2047 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2053 spin_lock_irqsave(&dbri->lock, flags);
2058 spin_unlock_irqrestore(&dbri->lock, flags);
2068 cs4215_open(dbri);
2075 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2076 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2089 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2090 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2095 ret = cs4215_prepare(dbri, params_rate(hw_params),
2110 dma_map_single(&dbri->op->dev,
2124 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2125 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2138 dma_unmap_single(&dbri->op->dev, info->dvma_buffer,
2143 reset_pipe(dbri, info->pipe);
2152 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2153 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2162 spin_lock_irq(&dbri->lock);
2168 ret = setup_descs(dbri, DBRI_STREAMNO(substream),
2171 spin_unlock_irq(&dbri->lock);
2179 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2180 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2188 xmit_descs(dbri);
2192 reset_pipe(dbri, info->pipe);
2203 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2204 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2269 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2272 if (snd_BUG_ON(!dbri))
2274 info = &dbri->stream_info[kcontrol->private_value];
2284 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2286 &dbri->stream_info[kcontrol->private_value];
2312 cs4215_setdata(dbri, 1);
2314 cs4215_setdata(dbri, 0);
2335 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2341 if (snd_BUG_ON(!dbri))
2346 (dbri->mm.data[elem] >> shift) & mask;
2349 (dbri->mm.ctrl[elem - 4] >> shift) & mask;
2360 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2368 if (snd_BUG_ON(!dbri))
2377 dbri->mm.data[elem] = (dbri->mm.data[elem] &
2379 changed = (val != dbri->mm.data[elem]);
2381 dbri->mm.ctrl[elem - 4] = (dbri->mm.ctrl[elem - 4] &
2383 changed = (val != dbri->mm.ctrl[elem - 4]);
2389 dbri->mm.data[elem & 3]);
2395 cs4215_setdata(dbri, 1);
2397 cs4215_setdata(dbri, 0);
2443 struct snd_dbri *dbri;
2447 dbri = card->private_data;
2453 snd_ctl_new1(&dbri_controls[idx], dbri));
2459 dbri->stream_info[idx].left_gain = 0;
2460 dbri->stream_info[idx].right_gain = 0;
2472 struct snd_dbri *dbri = entry->private_data;
2474 snd_iprintf(buffer, "REG0: 0x%x\n", sbus_readl(dbri->regs + REG0));
2475 snd_iprintf(buffer, "REG2: 0x%x\n", sbus_readl(dbri->regs + REG2));
2476 snd_iprintf(buffer, "REG8: 0x%x\n", sbus_readl(dbri->regs + REG8));
2477 snd_iprintf(buffer, "REG9: 0x%x\n", sbus_readl(dbri->regs + REG9));
2484 struct snd_dbri *dbri = entry->private_data;
2489 if (pipe_active(dbri, pipe)) {
2490 struct dbri_pipe *pptr = &dbri->pipes[pipe];
2506 struct snd_dbri *dbri = card->private_data;
2508 snd_card_ro_proc_new(card, "regs", dbri, dbri_regs_read);
2510 snd_card_ro_proc_new(card, "debug", dbri, dbri_debug_read);
2519 static void snd_dbri_free(struct snd_dbri *dbri);
2525 struct snd_dbri *dbri = card->private_data;
2528 spin_lock_init(&dbri->lock);
2529 dbri->op = op;
2530 dbri->irq = irq;
2532 dbri->dma = dma_alloc_coherent(&op->dev, sizeof(struct dbri_dma),
2533 &dbri->dma_dvma, GFP_KERNEL);
2534 if (!dbri->dma)
2538 dbri->dma, dbri->dma_dvma);
2541 dbri->regs_size = resource_size(&op->resource[0]);
2542 dbri->regs = of_ioremap(&op->resource[0], 0,
2543 dbri->regs_size, "DBRI Registers");
2544 if (!dbri->regs) {
2547 (void *)dbri->dma, dbri->dma_dvma);
2551 err = request_irq(dbri->irq, snd_dbri_interrupt, IRQF_SHARED,
2552 "DBRI audio", dbri);
2554 printk(KERN_ERR "DBRI: Can't get irq %d\n", dbri->irq);
2555 of_iounmap(&op->resource[0], dbri->regs, dbri->regs_size);
2557 (void *)dbri->dma, dbri->dma_dvma);
2562 dbri_initialize(dbri);
2563 err = cs4215_init(dbri);
2565 snd_dbri_free(dbri);
2572 static void snd_dbri_free(struct snd_dbri *dbri)
2575 dbri_reset(dbri);
2577 if (dbri->irq)
2578 free_irq(dbri->irq, dbri);
2580 if (dbri->regs)
2581 of_iounmap(&dbri->op->resource[0], dbri->regs, dbri->regs_size);
2583 if (dbri->dma)
2584 dma_free_coherent(&dbri->op->dev,
2586 (void *)dbri->dma, dbri->dma_dvma);
2591 struct snd_dbri *dbri;
2629 dbri = card->private_data;
2647 dev, dbri->regs,
2648 dbri->irq, op->dev.of_node->name[9], dbri->mm.version);
2654 snd_dbri_free(dbri);
2681 .name = "dbri",