Lines Matching defs:msp
114 static void set_prot_desc_tx(struct ux500_msp *msp,
124 if (msp->def_elem_len) {
138 writel(temp_reg, msp->registers + MSP_TCF);
141 static void set_prot_desc_rx(struct ux500_msp *msp,
151 if (msp->def_elem_len) {
166 writel(temp_reg, msp->registers + MSP_RCF);
169 static int configure_protocol(struct ux500_msp *msp,
177 msp->def_elem_len = config->def_elem_len;
180 dev_err(msp->dev, "%s: ERROR: Invalid protocol!\n",
191 dev_err(msp->dev,
198 set_prot_desc_tx(msp, protdesc, data_size);
200 set_prot_desc_rx(msp, protdesc, data_size);
203 temp_reg = readl(msp->registers + MSP_GCR) & ~TX_CLK_POL_RISING;
205 writel(temp_reg, msp->registers + MSP_GCR);
206 temp_reg = readl(msp->registers + MSP_GCR) & ~RX_CLK_POL_RISING;
208 writel(temp_reg, msp->registers + MSP_GCR);
213 static int setup_bitclk(struct ux500_msp *msp, struct ux500_msp_config *config)
222 reg_val_GCR = readl(msp->registers + MSP_GCR);
223 writel(reg_val_GCR & ~SRG_ENABLE, msp->registers + MSP_GCR);
246 dev_err(msp->dev, "%s: ERROR: Unknown protocol (%d)!\n",
255 writel(temp_reg, msp->registers + MSP_SRG);
257 msp->f_bitclk = (config->f_inputclk)/(sck_div + 1);
261 reg_val_GCR = readl(msp->registers + MSP_GCR);
262 writel(reg_val_GCR | SRG_ENABLE, msp->registers + MSP_GCR);
268 static int configure_multichannel(struct ux500_msp *msp,
277 dev_err(msp->dev,
291 reg_val_MCR = readl(msp->registers + MSP_MCR);
294 msp->registers + MSP_MCR);
296 msp->registers + MSP_TCE0);
298 msp->registers + MSP_TCE1);
300 msp->registers + MSP_TCE2);
302 msp->registers + MSP_TCE3);
304 dev_err(msp->dev,
312 reg_val_MCR = readl(msp->registers + MSP_MCR);
315 msp->registers + MSP_MCR);
317 msp->registers + MSP_RCE0);
319 msp->registers + MSP_RCE1);
321 msp->registers + MSP_RCE2);
323 msp->registers + MSP_RCE3);
325 dev_err(msp->dev,
331 reg_val_MCR = readl(msp->registers + MSP_MCR);
334 msp->registers + MSP_MCR);
337 msp->registers + MSP_RCM);
339 msp->registers + MSP_RCV);
347 static int enable_msp(struct ux500_msp *msp, struct ux500_msp_config *config)
352 /* Configure msp with protocol dependent settings */
353 configure_protocol(msp, config);
354 setup_bitclk(msp, config);
356 status = configure_multichannel(msp, config);
358 dev_warn(msp->dev,
363 reg_val_DMACR = readl(msp->registers + MSP_DMACR);
368 writel(reg_val_DMACR, msp->registers + MSP_DMACR);
370 writel(config->iodelay, msp->registers + MSP_IODLY);
373 reg_val_GCR = readl(msp->registers + MSP_GCR);
374 writel(reg_val_GCR | FRAME_GEN_ENABLE, msp->registers + MSP_GCR);
379 static void flush_fifo_rx(struct ux500_msp *msp)
384 reg_val_GCR = readl(msp->registers + MSP_GCR);
385 writel(reg_val_GCR | RX_ENABLE, msp->registers + MSP_GCR);
387 reg_val_FLR = readl(msp->registers + MSP_FLR);
389 readl(msp->registers + MSP_DR);
390 reg_val_FLR = readl(msp->registers + MSP_FLR);
393 writel(reg_val_GCR, msp->registers + MSP_GCR);
396 static void flush_fifo_tx(struct ux500_msp *msp)
401 reg_val_GCR = readl(msp->registers + MSP_GCR);
402 writel(reg_val_GCR | TX_ENABLE, msp->registers + MSP_GCR);
403 writel(MSP_ITCR_ITEN | MSP_ITCR_TESTFIFO, msp->registers + MSP_ITCR);
405 reg_val_FLR = readl(msp->registers + MSP_FLR);
407 readl(msp->registers + MSP_TSTDR);
408 reg_val_FLR = readl(msp->registers + MSP_FLR);
410 writel(0x0, msp->registers + MSP_ITCR);
411 writel(reg_val_GCR, msp->registers + MSP_GCR);
414 int ux500_msp_i2s_open(struct ux500_msp *msp,
422 dev_err(msp->dev,
431 dev_err(msp->dev, "%s: Error: No direction selected!\n",
436 tx_busy = (msp->dir_busy & MSP_DIR_TX) > 0;
437 rx_busy = (msp->dir_busy & MSP_DIR_RX) > 0;
439 dev_err(msp->dev, "%s: Error: TX is in use!\n", __func__);
443 dev_err(msp->dev, "%s: Error: RX is in use!\n", __func__);
447 msp->dir_busy |= (tx_sel ? MSP_DIR_TX : 0) | (rx_sel ? MSP_DIR_RX : 0);
462 old_reg = readl(msp->registers + MSP_GCR);
465 writel(new_reg, msp->registers + MSP_GCR);
467 res = enable_msp(msp, config);
469 dev_err(msp->dev, "%s: ERROR: enable_msp failed (%d)!\n",
474 msp->loopback_enable = 1;
477 flush_fifo_tx(msp);
478 flush_fifo_rx(msp);
480 msp->msp_state = MSP_STATE_CONFIGURED;
484 static void disable_msp_rx(struct ux500_msp *msp)
488 reg_val_GCR = readl(msp->registers + MSP_GCR);
489 writel(reg_val_GCR & ~RX_ENABLE, msp->registers + MSP_GCR);
490 reg_val_DMACR = readl(msp->registers + MSP_DMACR);
491 writel(reg_val_DMACR & ~RX_DMA_ENABLE, msp->registers + MSP_DMACR);
492 reg_val_IMSC = readl(msp->registers + MSP_IMSC);
495 msp->registers + MSP_IMSC);
497 msp->dir_busy &= ~MSP_DIR_RX;
500 static void disable_msp_tx(struct ux500_msp *msp)
504 reg_val_GCR = readl(msp->registers + MSP_GCR);
505 writel(reg_val_GCR & ~TX_ENABLE, msp->registers + MSP_GCR);
506 reg_val_DMACR = readl(msp->registers + MSP_DMACR);
507 writel(reg_val_DMACR & ~TX_DMA_ENABLE, msp->registers + MSP_DMACR);
508 reg_val_IMSC = readl(msp->registers + MSP_IMSC);
511 msp->registers + MSP_IMSC);
513 msp->dir_busy &= ~MSP_DIR_TX;
516 static int disable_msp(struct ux500_msp *msp, unsigned int dir)
521 reg_val_GCR = readl(msp->registers + MSP_GCR);
525 reg_val_GCR = readl(msp->registers + MSP_GCR);
527 msp->registers + MSP_GCR);
530 flush_fifo_tx(msp);
533 writel((readl(msp->registers + MSP_GCR) &
534 (~TX_ENABLE)), msp->registers + MSP_GCR);
537 flush_fifo_rx(msp);
540 writel((readl(msp->registers + MSP_GCR) &
542 msp->registers + MSP_GCR);
544 disable_msp_tx(msp);
545 disable_msp_rx(msp);
547 disable_msp_tx(msp);
549 disable_msp_rx(msp);
554 int ux500_msp_i2s_trigger(struct ux500_msp *msp, int cmd, int direction)
558 if (msp->msp_state == MSP_STATE_IDLE) {
559 dev_err(msp->dev, "%s: ERROR: MSP is not configured!\n",
572 reg_val_GCR = readl(msp->registers + MSP_GCR);
573 writel(reg_val_GCR | enable_bit, msp->registers + MSP_GCR);
580 disable_msp_tx(msp);
582 disable_msp_rx(msp);
591 int ux500_msp_i2s_close(struct ux500_msp *msp, unsigned int dir)
595 dev_dbg(msp->dev, "%s: Enter (dir = 0x%01x).\n", __func__, dir);
597 status = disable_msp(msp, dir);
598 if (msp->dir_busy == 0) {
600 msp->msp_state = MSP_STATE_IDLE;
601 writel((readl(msp->registers + MSP_GCR) &
603 msp->registers + MSP_GCR);
605 writel(0, msp->registers + MSP_GCR);
606 writel(0, msp->registers + MSP_TCF);
607 writel(0, msp->registers + MSP_RCF);
608 writel(0, msp->registers + MSP_DMACR);
609 writel(0, msp->registers + MSP_SRG);
610 writel(0, msp->registers + MSP_MCR);
611 writel(0, msp->registers + MSP_RCM);
612 writel(0, msp->registers + MSP_RCV);
613 writel(0, msp->registers + MSP_TCE0);
614 writel(0, msp->registers + MSP_TCE1);
615 writel(0, msp->registers + MSP_TCE2);
616 writel(0, msp->registers + MSP_TCE3);
617 writel(0, msp->registers + MSP_RCE0);
618 writel(0, msp->registers + MSP_RCE1);
619 writel(0, msp->registers + MSP_RCE2);
620 writel(0, msp->registers + MSP_RCE3);
631 struct ux500_msp *msp;
634 msp = *msp_p;
635 if (!msp)
638 msp->dev = &pdev->dev;
647 msp->tx_rx_addr = res->start + MSP_DR;
648 msp->registers = devm_ioremap(&pdev->dev, res->start,
650 if (msp->registers == NULL) {
655 msp->msp_state = MSP_STATE_IDLE;
656 msp->loopback_enable = 0;
662 struct ux500_msp *msp)
664 dev_dbg(msp->dev, "%s: Enter (id = %d).\n", __func__, msp->id);