Lines Matching defs:mcbsp
3 * omap-mcbsp.c -- OMAP ALSA SoC DAI driver using McBSP port
24 #include "omap-mcbsp-priv.h"
25 #include "omap-mcbsp.h"
39 static void omap_mcbsp_dump_reg(struct omap_mcbsp *mcbsp)
41 dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
42 dev_dbg(mcbsp->dev, "DRR2: 0x%04x\n", MCBSP_READ(mcbsp, DRR2));
43 dev_dbg(mcbsp->dev, "DRR1: 0x%04x\n", MCBSP_READ(mcbsp, DRR1));
44 dev_dbg(mcbsp->dev, "DXR2: 0x%04x\n", MCBSP_READ(mcbsp, DXR2));
45 dev_dbg(mcbsp->dev, "DXR1: 0x%04x\n", MCBSP_READ(mcbsp, DXR1));
46 dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n", MCBSP_READ(mcbsp, SPCR2));
47 dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n", MCBSP_READ(mcbsp, SPCR1));
48 dev_dbg(mcbsp->dev, "RCR2: 0x%04x\n", MCBSP_READ(mcbsp, RCR2));
49 dev_dbg(mcbsp->dev, "RCR1: 0x%04x\n", MCBSP_READ(mcbsp, RCR1));
50 dev_dbg(mcbsp->dev, "XCR2: 0x%04x\n", MCBSP_READ(mcbsp, XCR2));
51 dev_dbg(mcbsp->dev, "XCR1: 0x%04x\n", MCBSP_READ(mcbsp, XCR1));
52 dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n", MCBSP_READ(mcbsp, SRGR2));
53 dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n", MCBSP_READ(mcbsp, SRGR1));
54 dev_dbg(mcbsp->dev, "PCR0: 0x%04x\n", MCBSP_READ(mcbsp, PCR0));
55 dev_dbg(mcbsp->dev, "***********************\n");
58 static int omap2_mcbsp_set_clks_src(struct omap_mcbsp *mcbsp, u8 fck_src_id)
71 fck_src = clk_get(mcbsp->dev, src);
73 dev_info(mcbsp->dev, "CLKS: could not clk_get() %s\n", src);
77 if (mcbsp->active)
78 pm_runtime_put_sync(mcbsp->dev);
80 r = clk_set_parent(mcbsp->fclk, fck_src);
82 dev_err(mcbsp->dev, "CLKS: could not clk_set_parent() to %s\n",
85 if (mcbsp->active)
86 pm_runtime_get_sync(mcbsp->dev);
95 struct omap_mcbsp *mcbsp = data;
98 irqst = MCBSP_READ(mcbsp, IRQST);
99 dev_dbg(mcbsp->dev, "IRQ callback : 0x%x\n", irqst);
102 dev_err(mcbsp->dev, "RX Frame Sync Error!\n");
104 dev_dbg(mcbsp->dev, "RX Frame Sync\n");
106 dev_dbg(mcbsp->dev, "RX End Of Frame\n");
108 dev_dbg(mcbsp->dev, "RX Buffer Threshold Reached\n");
110 dev_err(mcbsp->dev, "RX Buffer Underflow!\n");
112 dev_err(mcbsp->dev, "RX Buffer Overflow!\n");
115 dev_err(mcbsp->dev, "TX Frame Sync Error!\n");
117 dev_dbg(mcbsp->dev, "TX Frame Sync\n");
119 dev_dbg(mcbsp->dev, "TX End Of Frame\n");
121 dev_dbg(mcbsp->dev, "TX Buffer threshold Reached\n");
123 dev_err(mcbsp->dev, "TX Buffer Underflow!\n");
125 dev_err(mcbsp->dev, "TX Buffer Overflow!\n");
127 dev_dbg(mcbsp->dev, "TX Buffer empty at end of frame\n");
129 MCBSP_WRITE(mcbsp, IRQST, irqst);
136 struct omap_mcbsp *mcbsp = data;
139 irqst_spcr2 = MCBSP_READ(mcbsp, SPCR2);
140 dev_dbg(mcbsp->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2);
143 dev_err(mcbsp->dev, "TX Frame Sync Error! : 0x%x\n",
146 MCBSP_WRITE(mcbsp, SPCR2, MCBSP_READ_CACHE(mcbsp, SPCR2));
154 struct omap_mcbsp *mcbsp = data;
157 irqst_spcr1 = MCBSP_READ(mcbsp, SPCR1);
158 dev_dbg(mcbsp->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1);
161 dev_err(mcbsp->dev, "RX Frame Sync Error! : 0x%x\n",
164 MCBSP_WRITE(mcbsp, SPCR1, MCBSP_READ_CACHE(mcbsp, SPCR1));
176 static void omap_mcbsp_config(struct omap_mcbsp *mcbsp,
179 dev_dbg(mcbsp->dev, "Configuring McBSP%d phys_base: 0x%08lx\n",
180 mcbsp->id, mcbsp->phys_base);
183 MCBSP_WRITE(mcbsp, SPCR2, config->spcr2);
184 MCBSP_WRITE(mcbsp, SPCR1, config->spcr1);
185 MCBSP_WRITE(mcbsp, RCR2, config->rcr2);
186 MCBSP_WRITE(mcbsp, RCR1, config->rcr1);
187 MCBSP_WRITE(mcbsp, XCR2, config->xcr2);
188 MCBSP_WRITE(mcbsp, XCR1, config->xcr1);
189 MCBSP_WRITE(mcbsp, SRGR2, config->srgr2);
190 MCBSP_WRITE(mcbsp, SRGR1, config->srgr1);
191 MCBSP_WRITE(mcbsp, MCR2, config->mcr2);
192 MCBSP_WRITE(mcbsp, MCR1, config->mcr1);
193 MCBSP_WRITE(mcbsp, PCR0, config->pcr0);
194 if (mcbsp->pdata->has_ccr) {
195 MCBSP_WRITE(mcbsp, XCCR, config->xccr);
196 MCBSP_WRITE(mcbsp, RCCR, config->rccr);
199 if (mcbsp->pdata->has_wakeup)
200 MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
203 if (mcbsp->irq)
204 MCBSP_WRITE(mcbsp, IRQEN, RSYNCERREN | XSYNCERREN |
209 * omap_mcbsp_dma_reg_params - returns the address of mcbsp data register
210 * @mcbsp: omap_mcbsp struct for the McBSP instance
213 * Returns the address of mcbsp data transmit register or data receive register
216 static int omap_mcbsp_dma_reg_params(struct omap_mcbsp *mcbsp,
222 if (mcbsp->pdata->reg_size == 2)
227 if (mcbsp->pdata->reg_size == 2)
233 return mcbsp->phys_dma_base + data_reg * mcbsp->pdata->reg_step;
241 static void omap_mcbsp_set_tx_threshold(struct omap_mcbsp *mcbsp, u16 threshold)
243 if (threshold && threshold <= mcbsp->max_tx_thres)
244 MCBSP_WRITE(mcbsp, THRSH2, threshold - 1);
252 static void omap_mcbsp_set_rx_threshold(struct omap_mcbsp *mcbsp, u16 threshold)
254 if (threshold && threshold <= mcbsp->max_rx_thres)
255 MCBSP_WRITE(mcbsp, THRSH1, threshold - 1);
261 static u16 omap_mcbsp_get_tx_delay(struct omap_mcbsp *mcbsp)
266 buffstat = MCBSP_READ(mcbsp, XBUFFSTAT);
269 return mcbsp->pdata->buffer_size - buffstat;
276 static u16 omap_mcbsp_get_rx_delay(struct omap_mcbsp *mcbsp)
281 buffstat = MCBSP_READ(mcbsp, RBUFFSTAT);
283 threshold = MCBSP_READ(mcbsp, THRSH1);
292 static int omap_mcbsp_request(struct omap_mcbsp *mcbsp)
297 reg_cache = kzalloc(mcbsp->reg_cache_size, GFP_KERNEL);
301 spin_lock(&mcbsp->lock);
302 if (!mcbsp->free) {
303 dev_err(mcbsp->dev, "McBSP%d is currently in use\n", mcbsp->id);
308 mcbsp->free = false;
309 mcbsp->reg_cache = reg_cache;
310 spin_unlock(&mcbsp->lock);
312 if(mcbsp->pdata->ops && mcbsp->pdata->ops->request)
313 mcbsp->pdata->ops->request(mcbsp->id - 1);
319 MCBSP_WRITE(mcbsp, SPCR1, 0);
320 MCBSP_WRITE(mcbsp, SPCR2, 0);
322 if (mcbsp->irq) {
323 err = request_irq(mcbsp->irq, omap_mcbsp_irq_handler, 0,
324 "McBSP", (void *)mcbsp);
326 dev_err(mcbsp->dev, "Unable to request IRQ\n");
330 err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler, 0,
331 "McBSP TX", (void *)mcbsp);
333 dev_err(mcbsp->dev, "Unable to request TX IRQ\n");
337 err = request_irq(mcbsp->rx_irq, omap_mcbsp_rx_irq_handler, 0,
338 "McBSP RX", (void *)mcbsp);
340 dev_err(mcbsp->dev, "Unable to request RX IRQ\n");
347 free_irq(mcbsp->tx_irq, (void *)mcbsp);
349 if(mcbsp->pdata->ops && mcbsp->pdata->ops->free)
350 mcbsp->pdata->ops->free(mcbsp->id - 1);
353 if (mcbsp->pdata->has_wakeup)
354 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
356 spin_lock(&mcbsp->lock);
357 mcbsp->free = true;
358 mcbsp->reg_cache = NULL;
360 spin_unlock(&mcbsp->lock);
366 static void omap_mcbsp_free(struct omap_mcbsp *mcbsp)
370 if(mcbsp->pdata->ops && mcbsp->pdata->ops->free)
371 mcbsp->pdata->ops->free(mcbsp->id - 1);
374 if (mcbsp->pdata->has_wakeup)
375 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
378 if (mcbsp->irq) {
379 MCBSP_WRITE(mcbsp, IRQEN, 0);
381 free_irq(mcbsp->irq, (void *)mcbsp);
383 free_irq(mcbsp->rx_irq, (void *)mcbsp);
384 free_irq(mcbsp->tx_irq, (void *)mcbsp);
387 reg_cache = mcbsp->reg_cache;
397 omap2_mcbsp_set_clks_src(mcbsp, MCBSP_CLKS_PRCM_SRC);
399 spin_lock(&mcbsp->lock);
400 if (mcbsp->free)
401 dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id);
403 mcbsp->free = true;
404 mcbsp->reg_cache = NULL;
405 spin_unlock(&mcbsp->lock);
415 static void omap_mcbsp_start(struct omap_mcbsp *mcbsp, int stream)
422 if (mcbsp->st_data)
423 omap_mcbsp_st_start(mcbsp);
426 w = MCBSP_READ_CACHE(mcbsp, PCR0);
428 enable_srg = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
429 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
433 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
434 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6));
439 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
440 MCBSP_WRITE(mcbsp, SPCR2, w | tx);
443 w = MCBSP_READ_CACHE(mcbsp, SPCR1);
444 MCBSP_WRITE(mcbsp, SPCR1, w | rx);
456 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
457 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7));
460 if (mcbsp->pdata->has_ccr) {
462 w = MCBSP_READ_CACHE(mcbsp, XCCR);
464 MCBSP_WRITE(mcbsp, XCCR, w);
465 w = MCBSP_READ_CACHE(mcbsp, RCCR);
467 MCBSP_WRITE(mcbsp, RCCR, w);
471 omap_mcbsp_dump_reg(mcbsp);
474 static void omap_mcbsp_stop(struct omap_mcbsp *mcbsp, int stream)
483 if (mcbsp->pdata->has_ccr) {
484 w = MCBSP_READ_CACHE(mcbsp, XCCR);
486 MCBSP_WRITE(mcbsp, XCCR, w);
488 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
489 MCBSP_WRITE(mcbsp, SPCR2, w & ~tx);
493 if (mcbsp->pdata->has_ccr) {
494 w = MCBSP_READ_CACHE(mcbsp, RCCR);
496 MCBSP_WRITE(mcbsp, RCCR, w);
498 w = MCBSP_READ_CACHE(mcbsp, SPCR1);
499 MCBSP_WRITE(mcbsp, SPCR1, w & ~rx);
501 idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
502 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
506 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
507 MCBSP_WRITE(mcbsp, SPCR2, w & ~(1 << 6));
510 if (mcbsp->st_data)
511 omap_mcbsp_st_stop(mcbsp);
514 #define max_thres(m) (mcbsp->pdata->buffer_size)
520 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
522 return sysfs_emit(buf, "%u\n", mcbsp->prop); \
529 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
537 if (!valid_threshold(mcbsp, val)) \
540 mcbsp->prop = val; \
556 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
561 dma_op_mode = mcbsp->dma_op_mode;
578 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
585 spin_lock_irq(&mcbsp->lock);
586 if (!mcbsp->free) {
590 mcbsp->dma_op_mode = i;
593 spin_unlock_irq(&mcbsp->lock);
617 struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
621 spin_lock_init(&mcbsp->lock);
622 mcbsp->free = true;
628 mcbsp->io_base = devm_ioremap_resource(&pdev->dev, res);
629 if (IS_ERR(mcbsp->io_base))
630 return PTR_ERR(mcbsp->io_base);
632 mcbsp->phys_base = res->start;
633 mcbsp->reg_cache_size = resource_size(res);
637 mcbsp->phys_dma_base = mcbsp->phys_base;
639 mcbsp->phys_dma_base = res->start;
648 mcbsp->irq = platform_get_irq_byname(pdev, "common");
649 if (mcbsp->irq == -ENXIO) {
650 mcbsp->tx_irq = platform_get_irq_byname(pdev, "tx");
652 if (mcbsp->tx_irq == -ENXIO) {
653 mcbsp->irq = platform_get_irq(pdev, 0);
654 mcbsp->tx_irq = 0;
656 mcbsp->rx_irq = platform_get_irq_byname(pdev, "rx");
657 mcbsp->irq = 0;
667 mcbsp->dma_req[0] = res->start;
668 mcbsp->dma_data[0].filter_data = &mcbsp->dma_req[0];
675 mcbsp->dma_req[1] = res->start;
676 mcbsp->dma_data[1].filter_data = &mcbsp->dma_req[1];
678 mcbsp->dma_data[0].filter_data = "tx";
679 mcbsp->dma_data[1].filter_data = "rx";
682 mcbsp->dma_data[0].addr = omap_mcbsp_dma_reg_params(mcbsp,
684 mcbsp->dma_data[1].addr = omap_mcbsp_dma_reg_params(mcbsp,
687 mcbsp->fclk = devm_clk_get(&pdev->dev, "fck");
688 if (IS_ERR(mcbsp->fclk)) {
689 ret = PTR_ERR(mcbsp->fclk);
690 dev_err(mcbsp->dev, "unable to get fck: %d\n", ret);
694 mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
695 if (mcbsp->pdata->buffer_size) {
704 mcbsp->max_tx_thres = max_thres(mcbsp) - 0x10;
705 mcbsp->max_rx_thres = max_thres(mcbsp) - 0x10;
707 ret = devm_device_add_group(mcbsp->dev, &additional_attr_group);
709 dev_err(mcbsp->dev,
727 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
731 if (mcbsp->pdata->buffer_size == 0)
747 omap_mcbsp_set_tx_threshold(mcbsp, words);
749 omap_mcbsp_set_rx_threshold(mcbsp, words);
759 struct omap_mcbsp *mcbsp = rule->private;
764 size = mcbsp->pdata->buffer_size;
774 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
778 err = omap_mcbsp_request(mcbsp);
795 if (mcbsp->pdata->buffer_size) {
805 mcbsp,
819 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
824 if (mcbsp->latency[stream2])
825 cpu_latency_qos_update_request(&mcbsp->pm_qos_req,
826 mcbsp->latency[stream2]);
827 else if (mcbsp->latency[stream1])
828 cpu_latency_qos_remove_request(&mcbsp->pm_qos_req);
830 mcbsp->latency[stream1] = 0;
833 omap_mcbsp_free(mcbsp);
834 mcbsp->configured = 0;
841 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
842 struct pm_qos_request *pm_qos_req = &mcbsp->pm_qos_req;
846 int latency = mcbsp->latency[stream2];
849 if (!latency || mcbsp->latency[stream1] < latency)
850 latency = mcbsp->latency[stream1];
863 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
869 mcbsp->active++;
870 omap_mcbsp_start(mcbsp, substream->stream);
876 omap_mcbsp_stop(mcbsp, substream->stream);
877 mcbsp->active--;
892 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
897 if (mcbsp->pdata->buffer_size == 0)
901 fifo_use = omap_mcbsp_get_tx_delay(mcbsp);
903 fifo_use = omap_mcbsp_get_rx_delay(mcbsp);
919 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
920 struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
925 unsigned int buffer_size = mcbsp->pdata->buffer_size;
943 if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) {
949 max_thrsh = mcbsp->max_tx_thres;
951 max_thrsh = mcbsp->max_rx_thres;
977 mcbsp->latency[substream->stream] = latency;
984 if (mcbsp->configured) {
993 format = mcbsp->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
1031 master = mcbsp->fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK;
1033 div = mcbsp->clk_div ? mcbsp->clk_div : 1;
1034 framesize = (mcbsp->in_freq / div) / params_rate(params);
1060 omap_mcbsp_config(mcbsp, &mcbsp->cfg_regs);
1061 mcbsp->wlen = wlen;
1062 mcbsp->configured = 1;
1074 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
1075 struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
1078 if (mcbsp->configured)
1081 mcbsp->fmt = fmt;
1087 if (!mcbsp->pdata->has_ccr) {
1093 if (mcbsp->pdata->has_ccr) {
1183 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
1184 struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
1189 mcbsp->clk_div = div;
1200 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
1201 struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
1204 if (mcbsp->active) {
1205 if (freq == mcbsp->in_freq)
1211 mcbsp->in_freq = freq;
1224 err = omap2_mcbsp_set_clks_src(mcbsp,
1232 err = omap2_mcbsp_set_clks_src(mcbsp,
1261 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(dai);
1263 pm_runtime_enable(mcbsp->dev);
1266 &mcbsp->dma_data[SNDRV_PCM_STREAM_PLAYBACK],
1267 &mcbsp->dma_data[SNDRV_PCM_STREAM_CAPTURE]);
1274 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(dai);
1276 pm_runtime_disable(mcbsp->dev);
1312 .name = "omap-mcbsp",
1343 .compatible = "ti,omap2420-mcbsp",
1347 .compatible = "ti,omap2430-mcbsp",
1351 .compatible = "ti,omap3-mcbsp",
1355 .compatible = "ti,omap4-mcbsp",
1365 struct omap_mcbsp *mcbsp;
1390 mcbsp = devm_kzalloc(&pdev->dev, sizeof(struct omap_mcbsp), GFP_KERNEL);
1391 if (!mcbsp)
1394 mcbsp->id = pdev->id;
1395 mcbsp->pdata = pdata;
1396 mcbsp->dev = &pdev->dev;
1397 platform_set_drvdata(pdev, mcbsp);
1403 if (mcbsp->pdata->reg_size == 2) {
1419 struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
1421 if (mcbsp->pdata->ops && mcbsp->pdata->ops->free)
1422 mcbsp->pdata->ops->free(mcbsp->id);
1424 if (cpu_latency_qos_request_active(&mcbsp->pm_qos_req))
1425 cpu_latency_qos_remove_request(&mcbsp->pm_qos_req);
1430 .name = "omap-mcbsp",
1443 MODULE_ALIAS("platform:omap-mcbsp");