Lines Matching defs:pll_rates
50 unsigned int pll_rates[2];
81 u32 pll_rates[2];
181 if (!(rate % 8000) && priv->pll_rates[J721E_CLK_PARENT_48000])
183 else if (!(rate % 11025) && priv->pll_rates[J721E_CLK_PARENT_44100])
191 if (priv->pll_rates[clk_id] / scki <= J721E_MAX_CLK_HSDIV) {
518 .pll_rates = {
527 .pll_rates = {
536 .pll_rates = {
567 priv->pll_rates[J721E_CLK_PARENT_44100] =
568 match_data->pll_rates[J721E_CLK_PARENT_44100];
570 priv->pll_rates[J721E_CLK_PARENT_44100] = clk_get_rate(pll);
576 priv->pll_rates[J721E_CLK_PARENT_48000] =
577 match_data->pll_rates[J721E_CLK_PARENT_48000];
579 priv->pll_rates[J721E_CLK_PARENT_48000] = clk_get_rate(pll);
583 if (!priv->pll_rates[J721E_CLK_PARENT_44100] &&
584 !priv->pll_rates[J721E_CLK_PARENT_48000]) {
589 if (priv->pll_rates[J721E_CLK_PARENT_44100])
590 pll_rate = priv->pll_rates[J721E_CLK_PARENT_44100];
592 pll_rate = priv->pll_rates[J721E_CLK_PARENT_48000];
597 if (priv->pll_rates[J721E_CLK_PARENT_48000])
598 pll_rate = priv->pll_rates[J721E_CLK_PARENT_48000];
600 pll_rate = priv->pll_rates[J721E_CLK_PARENT_44100];