Lines Matching defs:mcasp
42 #include "davinci-mcasp.h"
73 struct davinci_mcasp *mcasp;
133 static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset,
136 void __iomem *reg = mcasp->base + offset;
140 static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset,
143 void __iomem *reg = mcasp->base + offset;
147 static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset,
150 void __iomem *reg = mcasp->base + offset;
154 static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset,
157 __raw_writel(val, mcasp->base + offset);
160 static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset)
162 return (u32)__raw_readl(mcasp->base + offset);
165 static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val)
169 mcasp_set_bits(mcasp, ctl_reg, val);
174 if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val)
178 if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val))
182 static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp)
184 u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
185 u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
190 static inline void mcasp_set_clk_pdir(struct davinci_mcasp *mcasp, bool enable)
194 for_each_set_bit_from(bit, &mcasp->pdir, PIN_BIT_AFSR + 1) {
196 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
198 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
202 static inline void mcasp_set_axr_pdir(struct davinci_mcasp *mcasp, bool enable)
206 for_each_set_bit(bit, &mcasp->pdir, PIN_BIT_AMUTE) {
208 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
210 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
214 static void mcasp_start_rx(struct davinci_mcasp *mcasp)
216 if (mcasp->rxnumevt) { /* enable FIFO */
217 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
219 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
220 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
224 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
225 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
231 if (mcasp_is_synchronous(mcasp)) {
232 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
233 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
234 mcasp_set_clk_pdir(mcasp, true);
238 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
239 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
241 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
243 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
244 if (mcasp_is_synchronous(mcasp))
245 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
248 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
249 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
252 static void mcasp_start_tx(struct davinci_mcasp *mcasp)
256 if (mcasp->txnumevt) { /* enable FIFO */
257 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
259 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
260 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
264 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
265 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
266 mcasp_set_clk_pdir(mcasp, true);
269 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
270 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
274 while ((mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) & XRDATA) &&
278 mcasp_set_axr_pdir(mcasp, true);
281 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
283 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
286 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
287 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
290 static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream)
292 mcasp->streams++;
295 mcasp_start_tx(mcasp);
297 mcasp_start_rx(mcasp);
300 static void mcasp_stop_rx(struct davinci_mcasp *mcasp)
303 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
304 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
310 if (mcasp_is_synchronous(mcasp) && !mcasp->streams) {
311 mcasp_set_clk_pdir(mcasp, false);
312 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0);
315 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0);
316 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
318 if (mcasp->rxnumevt) { /* disable FIFO */
319 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
321 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
325 static void mcasp_stop_tx(struct davinci_mcasp *mcasp)
330 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
331 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
337 if (mcasp_is_synchronous(mcasp) && mcasp->streams)
340 mcasp_set_clk_pdir(mcasp, false);
343 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val);
344 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
346 if (mcasp->txnumevt) { /* disable FIFO */
347 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
349 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
352 mcasp_set_axr_pdir(mcasp, false);
355 static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream)
357 mcasp->streams--;
360 mcasp_stop_tx(mcasp);
362 mcasp_stop_rx(mcasp);
367 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
369 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK];
373 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG);
375 dev_warn(mcasp->dev, "Transmit buffer underflow\n");
378 substream = mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK];
384 dev_warn(mcasp->dev, "unhandled tx event. txstat: 0x%08x\n",
391 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, handled_mask);
398 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
400 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE];
404 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG);
406 dev_warn(mcasp->dev, "Receive buffer overflow\n");
409 substream = mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE];
415 dev_warn(mcasp->dev, "unhandled rx event. rxstat: 0x%08x\n",
422 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, handled_mask);
429 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
432 if (mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK])
435 if (mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE])
444 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
453 pm_runtime_get_sync(mcasp->dev);
456 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
457 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
463 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
464 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
470 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
471 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
480 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
481 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
490 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay),
492 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay),
498 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
499 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
501 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
502 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
505 set_bit(PIN_BIT_ACLKX, &mcasp->pdir);
506 set_bit(PIN_BIT_ACLKR, &mcasp->pdir);
508 set_bit(PIN_BIT_AFSX, &mcasp->pdir);
509 set_bit(PIN_BIT_AFSR, &mcasp->pdir);
511 mcasp->bclk_master = 1;
515 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
516 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
518 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
519 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
522 set_bit(PIN_BIT_ACLKX, &mcasp->pdir);
523 set_bit(PIN_BIT_ACLKR, &mcasp->pdir);
525 clear_bit(PIN_BIT_AFSX, &mcasp->pdir);
526 clear_bit(PIN_BIT_AFSR, &mcasp->pdir);
528 mcasp->bclk_master = 1;
532 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
533 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
535 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
536 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
539 clear_bit(PIN_BIT_ACLKX, &mcasp->pdir);
540 clear_bit(PIN_BIT_ACLKR, &mcasp->pdir);
542 set_bit(PIN_BIT_AFSX, &mcasp->pdir);
543 set_bit(PIN_BIT_AFSR, &mcasp->pdir);
545 mcasp->bclk_master = 0;
549 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
550 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
552 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
553 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
556 clear_bit(PIN_BIT_ACLKX, &mcasp->pdir);
557 clear_bit(PIN_BIT_ACLKR, &mcasp->pdir);
559 clear_bit(PIN_BIT_AFSX, &mcasp->pdir);
560 clear_bit(PIN_BIT_AFSR, &mcasp->pdir);
562 mcasp->bclk_master = 0;
571 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
572 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
576 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
577 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
581 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
582 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
586 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
587 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
599 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
600 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
602 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
603 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
606 mcasp->dai_fmt = fmt;
608 pm_runtime_put(mcasp->dev);
612 static int __davinci_mcasp_set_clkdiv(struct davinci_mcasp *mcasp, int div_id,
615 pm_runtime_get_sync(mcasp->dev);
618 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
620 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
625 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG,
627 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG,
630 mcasp->bclk_div = div;
644 mcasp->slot_width = div / mcasp->tdm_slots;
645 if (div % mcasp->tdm_slots)
646 dev_warn(mcasp->dev,
648 __func__, div, mcasp->tdm_slots);
655 pm_runtime_put(mcasp->dev);
662 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
664 return __davinci_mcasp_set_clkdiv(mcasp, div_id, div, 1);
670 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
672 pm_runtime_get_sync(mcasp->dev);
677 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
679 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
681 clear_bit(PIN_BIT_AHCLKX, &mcasp->pdir);
684 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
686 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
688 set_bit(PIN_BIT_AHCLKX, &mcasp->pdir);
691 dev_err(mcasp->dev, "Invalid clk id: %d\n", clk_id);
696 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
697 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
698 set_bit(PIN_BIT_AHCLKX, &mcasp->pdir);
704 mcasp->sysclk_freq = freq;
706 pm_runtime_put(mcasp->dev);
711 static int davinci_mcasp_ch_constraint(struct davinci_mcasp *mcasp, int stream,
714 struct snd_pcm_hw_constraint_list *cl = &mcasp->chconstr[stream];
716 int slots = mcasp->tdm_slots;
719 if (mcasp->tdm_mask[stream])
720 slots = hweight32(mcasp->tdm_mask[stream]);
733 static int davinci_mcasp_set_ch_constraints(struct davinci_mcasp *mcasp)
737 for (i = 0; i < mcasp->num_serializer; i++)
738 if (mcasp->serial_dir[i] == TX_MODE)
740 else if (mcasp->serial_dir[i] == RX_MODE)
743 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_PLAYBACK,
748 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_CAPTURE,
760 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
762 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
765 dev_dbg(mcasp->dev,
770 dev_err(mcasp->dev,
778 dev_err(mcasp->dev, "%s: Unsupported slot_width %d\n",
783 mcasp->tdm_slots = slots;
784 mcasp->tdm_mask[SNDRV_PCM_STREAM_PLAYBACK] = tx_mask;
785 mcasp->tdm_mask[SNDRV_PCM_STREAM_CAPTURE] = rx_mask;
786 mcasp->slot_width = slot_width;
788 return davinci_mcasp_set_ch_constraints(mcasp);
791 static int davinci_config_channel_size(struct davinci_mcasp *mcasp,
798 if (mcasp->slot_width)
799 slot_width = mcasp->slot_width;
800 else if (mcasp->max_format_width)
801 slot_width = mcasp->max_format_width;
813 if ((mcasp->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) ==
825 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
826 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt),
828 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt),
830 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate),
832 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate),
834 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask);
845 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate),
847 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(15),
851 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask);
856 static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream,
859 struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream];
863 u8 slots = mcasp->tdm_slots;
869 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
875 if (mcasp->version < MCASP_VERSION_3)
876 mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
879 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
880 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
883 mcasp->active_serializers[SNDRV_PCM_STREAM_CAPTURE];
885 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
886 mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS);
888 mcasp->active_serializers[SNDRV_PCM_STREAM_PLAYBACK];
892 for (i = 0; i < mcasp->num_serializer; i++) {
893 mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
894 mcasp->serial_dir[i]);
895 if (mcasp->serial_dir[i] == TX_MODE &&
897 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
898 mcasp->dismod, DISMOD_MASK);
899 set_bit(PIN_BIT_AXR(i), &mcasp->pdir);
901 } else if (mcasp->serial_dir[i] == RX_MODE &&
903 clear_bit(PIN_BIT_AXR(i), &mcasp->pdir);
907 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
910 if (mcasp->serial_dir[i] != INACTIVE_MODE)
911 mcasp_mod_bits(mcasp,
913 mcasp->dismod, DISMOD_MASK);
914 clear_bit(PIN_BIT_AXR(i), &mcasp->pdir);
920 numevt = mcasp->txnumevt;
921 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
924 numevt = mcasp->rxnumevt;
925 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
929 dev_warn(mcasp->dev, "stream has more channels (%d) than are "
930 "enabled in mcasp (%d)\n", channels,
954 dev_err(mcasp->dev, "Invalid combination of period words and "
972 mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK);
973 mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK);
981 mcasp->active_serializers[stream] = active_serializers;
986 static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream,
995 total_slots = mcasp->tdm_slots;
1003 if (mcasp->tdm_mask[stream]) {
1004 active_slots = hweight32(mcasp->tdm_mask[stream]);
1009 if ((1 << i) & mcasp->tdm_mask[stream]) {
1026 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
1028 if (!mcasp->dat_port)
1032 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask);
1033 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD);
1034 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
1037 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask);
1038 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD);
1039 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG,
1046 if (mcasp_is_synchronous(mcasp) && !mcasp->channels)
1047 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
1055 static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp,
1058 u8 *cs_bytes = (u8 *)&mcasp->iec958_status;
1060 if (!mcasp->dat_port)
1061 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSEL);
1063 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSEL);
1066 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180));
1068 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, 0xFFFF);
1071 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
1074 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC);
1076 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
1109 dev_err(mcasp->dev, "unsupported sampling rate: %d\n", rate);
1113 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRA_REG, mcasp->iec958_status);
1114 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRB_REG, mcasp->iec958_status);
1117 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN);
1122 static int davinci_mcasp_calc_clk_div(struct davinci_mcasp *mcasp,
1126 u32 reg = mcasp_get_reg(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG);
1142 dev_warn(mcasp->dev, "Too fast reference clock (%u)\n",
1160 dev_info(mcasp->dev, "Sample-rate is off by %d PPM\n",
1163 __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_BCLK, div, 0);
1165 __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_AUXCLK,
1172 static inline u32 davinci_mcasp_tx_delay(struct davinci_mcasp *mcasp)
1174 if (!mcasp->txnumevt)
1177 return mcasp_get_reg(mcasp, mcasp->fifo_base + MCASP_WFIFOSTS_OFFSET);
1180 static inline u32 davinci_mcasp_rx_delay(struct davinci_mcasp *mcasp)
1182 if (!mcasp->rxnumevt)
1185 return mcasp_get_reg(mcasp, mcasp->fifo_base + MCASP_RFIFOSTS_OFFSET);
1192 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1196 fifo_use = davinci_mcasp_tx_delay(mcasp);
1198 fifo_use = davinci_mcasp_rx_delay(mcasp);
1212 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1245 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
1249 ret = davinci_mcasp_set_dai_fmt(cpu_dai, mcasp->dai_fmt);
1254 * If mcasp is BCLK master, and a BCLK divider was not provided by
1257 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
1258 int slots = mcasp->tdm_slots;
1263 if (mcasp->slot_width)
1264 sbits = mcasp->slot_width;
1266 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE)
1271 davinci_mcasp_calc_clk_div(mcasp, mcasp->sysclk_freq,
1275 ret = mcasp_common_hw_param(mcasp, substream->stream,
1280 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1281 ret = mcasp_dit_hw_param(mcasp, params_rate(params));
1283 ret = mcasp_i2s_hw_param(mcasp, substream->stream,
1289 davinci_config_channel_size(mcasp, word_length);
1291 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) {
1292 mcasp->channels = channels;
1293 if (!mcasp->max_format_width)
1294 mcasp->max_format_width = word_length;
1303 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1310 davinci_mcasp_start(mcasp, substream->stream);
1315 davinci_mcasp_stop(mcasp, substream->stream);
1335 slot_width = rd->mcasp->slot_width;
1358 format_width = rd->mcasp->max_format_width;
1385 int slots = rd->mcasp->tdm_slots;
1389 if (rd->mcasp->slot_width)
1390 sbits = rd->mcasp->slot_width;
1402 if (rd->mcasp->auxclk_fs_ratio)
1404 rd->mcasp->auxclk_fs_ratio;
1406 sysclk_freq = rd->mcasp->sysclk_freq;
1408 ppm = davinci_mcasp_calc_clk_div(rd->mcasp, sysclk_freq,
1420 dev_dbg(rd->mcasp->dev,
1435 int slots = rd->mcasp->tdm_slots;
1447 if (rd->mcasp->auxclk_fs_ratio)
1449 rd->mcasp->auxclk_fs_ratio;
1451 sysclk_freq = rd->mcasp->sysclk_freq;
1453 if (rd->mcasp->slot_width)
1454 sbits = rd->mcasp->slot_width;
1456 ppm = davinci_mcasp_calc_clk_div(rd->mcasp, sysclk_freq,
1465 dev_dbg(rd->mcasp->dev,
1489 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1491 &mcasp->ruledata[substream->stream];
1494 int tdm_slots = mcasp->tdm_slots;
1497 if (mcasp->substreams[substream->stream])
1500 mcasp->substreams[substream->stream] = substream;
1502 if (mcasp->tdm_mask[substream->stream])
1503 tdm_slots = hweight32(mcasp->tdm_mask[substream->stream]);
1505 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1517 for (i = 0; i < mcasp->num_serializer; i++) {
1518 if (mcasp->serial_dir[i] == dir)
1522 ruledata->mcasp = mcasp;
1531 if (mcasp->channels && mcasp->channels < max_channels &&
1533 max_channels = mcasp->channels;
1547 &mcasp->chconstr[substream->stream]);
1549 if (mcasp->max_format_width) {
1562 else if (mcasp->slot_width) {
1577 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
1605 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1607 mcasp->substreams[substream->stream] = NULL;
1608 mcasp->active_serializers[substream->stream] = 0;
1610 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1614 mcasp->channels = 0;
1615 mcasp->max_format_width = 0;
1632 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1634 memcpy(uctl->value.iec958.status, &mcasp->iec958_status,
1635 sizeof(mcasp->iec958_status));
1644 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1646 memcpy(&mcasp->iec958_status, uctl->value.iec958.status,
1647 sizeof(mcasp->iec958_status));
1656 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1658 memset(ucontrol->value.iec958.status, 0xff, sizeof(mcasp->iec958_status));
1680 static void davinci_mcasp_init_iec958_status(struct davinci_mcasp *mcasp)
1682 unsigned char *cs = (u8 *)&mcasp->iec958_status;
1692 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1696 snd_soc_dai_dma_data_set(dai, stream, &mcasp->dma_data[stream]);
1698 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) {
1699 davinci_mcasp_init_iec958_status(mcasp);
1735 .name = "davinci-mcasp.0",
1755 .name = "davinci-mcasp.1",
1770 .name = "davinci-mcasp",
1808 .compatible = "ti,dm646x-mcasp-audio",
1812 .compatible = "ti,da830-mcasp-audio",
1816 .compatible = "ti,am33xx-mcasp-audio",
1820 .compatible = "ti,dra7-mcasp-audio",
1824 .compatible = "ti,omap4-mcasp-audio",
1873 static bool davinci_mcasp_have_gpiochip(struct davinci_mcasp *mcasp)
1876 return of_property_read_bool(mcasp->dev->of_node, "gpio-controller");
1882 static int davinci_mcasp_get_config(struct davinci_mcasp *mcasp,
1909 mcasp->missing_audio_param = true;
1921 mcasp->missing_audio_param = true;
1940 mcasp->missing_audio_param = true;
1951 mcasp->auxclk_fs_ratio = val;
1965 mcasp->pdata = pdata;
1967 if (mcasp->missing_audio_param) {
1968 if (davinci_mcasp_have_gpiochip(mcasp)) {
1977 mcasp->op_mode = pdata->op_mode;
1979 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) {
1983 mcasp->tdm_slots = 2;
1987 mcasp->tdm_slots = 32;
1989 mcasp->tdm_slots = pdata->tdm_slots;
1992 mcasp->tdm_slots = 32;
1995 mcasp->num_serializer = pdata->num_serializer;
1997 mcasp->context.xrsr_regs = devm_kcalloc(&pdev->dev,
1998 mcasp->num_serializer, sizeof(u32),
2000 if (!mcasp->context.xrsr_regs)
2003 mcasp->serial_dir = pdata->serial_dir;
2004 mcasp->version = pdata->version;
2005 mcasp->txnumevt = pdata->txnumevt;
2006 mcasp->rxnumevt = pdata->rxnumevt;
2007 mcasp->dismod = pdata->dismod;
2019 static int davinci_mcasp_get_dma_type(struct davinci_mcasp *mcasp)
2025 if (!mcasp->dev->of_node)
2028 tmp = mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].filter_data;
2029 chan = dma_request_chan(mcasp->dev, tmp);
2031 return dev_err_probe(mcasp->dev, PTR_ERR(chan),
2042 dev_dbg(mcasp->dev, "DMA controller has no of-node\n");
2048 dev_dbg(mcasp->dev, "DMA controller compatible = \"%s\"\n", tmp);
2108 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
2110 if (mcasp->num_serializer && offset < mcasp->num_serializer &&
2111 mcasp->serial_dir[offset] != INACTIVE_MODE) {
2112 dev_err(mcasp->dev, "AXR%u pin is used for audio\n", offset);
2117 return pm_runtime_resume_and_get(mcasp->dev);
2122 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
2125 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset));
2128 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset));
2130 pm_runtime_put_sync(mcasp->dev);
2136 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
2140 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset));
2142 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset));
2144 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PFUNC_REG);
2147 mcasp_set_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset));
2150 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset));
2159 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
2162 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset));
2164 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset));
2170 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
2173 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PFUNC_REG);
2176 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset));
2179 mcasp_set_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset));
2187 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
2190 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDSET_REG);
2200 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
2203 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDIR_REG);
2223 static int davinci_mcasp_init_gpiochip(struct davinci_mcasp *mcasp)
2225 if (!davinci_mcasp_have_gpiochip(mcasp))
2228 mcasp->gpio_chip = davinci_mcasp_template_chip;
2229 mcasp->gpio_chip.label = dev_name(mcasp->dev);
2230 mcasp->gpio_chip.parent = mcasp->dev;
2232 return devm_gpiochip_add_data(mcasp->dev, &mcasp->gpio_chip, mcasp);
2236 static inline int davinci_mcasp_init_gpiochip(struct davinci_mcasp *mcasp)
2246 struct davinci_mcasp *mcasp;
2256 mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp),
2258 if (!mcasp)
2272 mcasp->base = devm_ioremap_resource(&pdev->dev, mem);
2273 if (IS_ERR(mcasp->base))
2274 return PTR_ERR(mcasp->base);
2276 dev_set_drvdata(&pdev->dev, mcasp);
2279 mcasp->dev = &pdev->dev;
2280 ret = davinci_mcasp_get_config(mcasp, pdev);
2285 pm_runtime_get_sync(mcasp->dev);
2286 mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000);
2287 pm_runtime_put(mcasp->dev);
2290 if (mcasp->missing_audio_param)
2304 irq_name, mcasp);
2310 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
2311 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
2324 IRQF_ONESHOT, irq_name, mcasp);
2330 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
2343 IRQF_ONESHOT, irq_name, mcasp);
2349 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
2354 mcasp->dat_port = true;
2356 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
2364 if (mcasp->version == MCASP_VERSION_OMAP)
2365 dma_data->addr += davinci_mcasp_txdma_offset(mcasp->pdata);
2367 dma_data->addr = mem->start + davinci_mcasp_txdma_offset(mcasp->pdata);
2372 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
2373 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
2379 mem->start + davinci_mcasp_rxdma_offset(mcasp->pdata);
2382 if (mcasp->version < MCASP_VERSION_3) {
2383 mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE;
2385 mcasp->dat_port = true;
2387 mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE;
2397 mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list =
2398 devm_kcalloc(mcasp->dev,
2399 32 + mcasp->num_serializer - 1,
2403 mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list =
2404 devm_kcalloc(mcasp->dev,
2405 32 + mcasp->num_serializer - 1,
2409 if (!mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list ||
2410 !mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list) {
2415 ret = davinci_mcasp_set_ch_constraints(mcasp);
2422 &davinci_mcasp_dai[mcasp->op_mode], 1);
2427 ret = davinci_mcasp_get_dma_type(mcasp);
2433 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE)
2454 ret = davinci_mcasp_init_gpiochip(mcasp);
2474 struct davinci_mcasp *mcasp = dev_get_drvdata(dev);
2475 struct davinci_mcasp_context *context = &mcasp->context;
2480 context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]);
2482 if (mcasp->txnumevt) {
2483 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
2484 context->afifo_regs[0] = mcasp_get_reg(mcasp, reg);
2486 if (mcasp->rxnumevt) {
2487 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
2488 context->afifo_regs[1] = mcasp_get_reg(mcasp, reg);
2491 for (i = 0; i < mcasp->num_serializer; i++)
2492 context->xrsr_regs[i] = mcasp_get_reg(mcasp,
2500 struct davinci_mcasp *mcasp = dev_get_drvdata(dev);
2501 struct davinci_mcasp_context *context = &mcasp->context;
2506 mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]);
2508 if (mcasp->txnumevt) {
2509 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
2510 mcasp_set_reg(mcasp, reg, context->afifo_regs[0]);
2512 if (mcasp->rxnumevt) {
2513 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
2514 mcasp_set_reg(mcasp, reg, context->afifo_regs[1]);
2517 for (i = 0; i < mcasp->num_serializer; i++)
2518 mcasp_set_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
2536 .name = "davinci-mcasp",