Lines Matching defs:mvc
53 struct tegra210_mvc *mvc = dev_get_drvdata(dev);
55 regmap_read(mvc->regmap, TEGRA210_MVC_CTRL, &(mvc->ctrl_value));
57 regcache_cache_only(mvc->regmap, true);
58 regcache_mark_dirty(mvc->regmap);
65 struct tegra210_mvc *mvc = dev_get_drvdata(dev);
67 regcache_cache_only(mvc->regmap, false);
68 regcache_sync(mvc->regmap);
70 regmap_write(mvc->regmap, TEGRA210_MVC_CTRL, mvc->ctrl_value);
71 regmap_update_bits(mvc->regmap,
93 static void tegra210_mvc_conv_vol(struct tegra210_mvc *mvc, u8 chan, s32 val)
101 if (mvc->curve_type == CURVE_POLY) {
104 mvc->volume[chan] = ((val * (1<<8)) / 100) << 16;
107 mvc->volume[chan] = (val * (1<<8)) / 100;
114 struct tegra210_mvc *mvc = snd_soc_component_get_drvdata(cmpnt);
118 regmap_read(mvc->regmap, TEGRA210_MVC_CTRL, &val);
179 struct tegra210_mvc *mvc = snd_soc_component_get_drvdata(cmpnt);
183 err = regmap_read_poll_timeout(mvc->regmap, TEGRA210_MVC_SWITCH,
199 struct tegra210_mvc *mvc = snd_soc_component_get_drvdata(cmpnt);
220 regmap_update_bits_check(mvc->regmap, TEGRA210_MVC_CTRL,
226 regmap_update_bits(mvc->regmap, TEGRA210_MVC_CTRL,
230 regmap_update_bits(mvc->regmap, TEGRA210_MVC_SWITCH,
265 struct tegra210_mvc *mvc = snd_soc_component_get_drvdata(cmpnt);
267 s32 val = mvc->volume[chan];
269 if (mvc->curve_type == CURVE_POLY) {
294 struct tegra210_mvc *mvc = snd_soc_component_get_drvdata(cmpnt);
296 int old_volume = mvc->volume[chan];
305 tegra210_mvc_conv_vol(mvc, chan, ucontrol->value.integer.value[0]);
307 if (mvc->volume[chan] == old_volume) {
313 regmap_update_bits(mvc->regmap, TEGRA210_MVC_CTRL,
317 regmap_update_bits(mvc->regmap, TEGRA210_MVC_CTRL,
321 mvc->volume[i] = mvc->volume[chan];
325 regmap_write(mvc->regmap,
327 mvc->volume[chan]);
329 regmap_write(mvc->regmap, mc->reg, mvc->volume[chan]);
331 regmap_update_bits(mvc->regmap, TEGRA210_MVC_SWITCH,
355 static void tegra210_mvc_reset_vol_settings(struct tegra210_mvc *mvc,
361 if (mvc->curve_type == CURVE_POLY) {
363 mvc->volume[i] = TEGRA210_MVC_INIT_VOL_DEFAULT_POLY;
366 mvc->volume[i] = TEGRA210_MVC_INIT_VOL_DEFAULT_LINEAR;
372 regmap_update_bits(mvc->regmap, TEGRA210_MVC_CTRL,
374 mvc->curve_type <<
379 regmap_write(mvc->regmap,
381 mvc->volume[i]);
382 regmap_write(mvc->regmap,
384 mvc->volume[i]);
388 regmap_update_bits(mvc->regmap, TEGRA210_MVC_SWITCH,
399 struct tegra210_mvc *mvc = snd_soc_component_get_drvdata(cmpnt);
401 ucontrol->value.enumerated.item[0] = mvc->curve_type;
410 struct tegra210_mvc *mvc = snd_soc_component_get_drvdata(cmpnt);
413 regmap_read(mvc->regmap, TEGRA210_MVC_ENABLE, &value);
420 if (mvc->curve_type == ucontrol->value.enumerated.item[0])
423 mvc->curve_type = ucontrol->value.enumerated.item[0];
425 tegra210_mvc_reset_vol_settings(mvc, cmpnt->dev);
430 static int tegra210_mvc_set_audio_cif(struct tegra210_mvc *mvc,
457 tegra_set_cif(mvc->regmap, reg, &cif_conf);
467 struct tegra210_mvc *mvc = snd_soc_dai_get_drvdata(dai);
476 regmap_write(mvc->regmap, TEGRA210_MVC_SOFT_RESET, 1);
478 err = regmap_read_poll_timeout(mvc->regmap, TEGRA210_MVC_SOFT_RESET,
486 err = tegra210_mvc_set_audio_cif(mvc, params, TEGRA210_MVC_RX_CIF_CTRL);
493 err = tegra210_mvc_set_audio_cif(mvc, params, TEGRA210_MVC_TX_CIF_CTRL);
499 tegra210_mvc_write_ram(mvc->regmap);
502 regmap_write(mvc->regmap, TEGRA210_MVC_POLY_N1, gain_params.poly_n1);
503 regmap_write(mvc->regmap, TEGRA210_MVC_POLY_N2, gain_params.poly_n2);
504 regmap_write(mvc->regmap, TEGRA210_MVC_DURATION, gain_params.duration);
507 regmap_write(mvc->regmap, TEGRA210_MVC_DURATION_INV,
702 { .compatible = "nvidia,tegra210-mvc" },
710 struct tegra210_mvc *mvc;
714 mvc = devm_kzalloc(dev, sizeof(*mvc), GFP_KERNEL);
715 if (!mvc)
718 dev_set_drvdata(dev, mvc);
720 mvc->curve_type = CURVE_LINEAR;
721 mvc->ctrl_value = TEGRA210_MVC_CTRL_DEFAULT;
727 mvc->regmap = devm_regmap_init_mmio(dev, regs,
729 if (IS_ERR(mvc->regmap)) {
731 return PTR_ERR(mvc->regmap);
734 regcache_cache_only(mvc->regmap, true);
746 tegra210_mvc_reset_vol_settings(mvc, &pdev->dev);
765 .name = "tegra210-mvc",