Lines Matching defs:i2s
50 struct tegra210_i2s *i2s = dev_get_drvdata(dev);
54 regmap_read(i2s->regmap, TEGRA210_I2S_CTRL, &val);
60 err = clk_set_rate(i2s->clk_i2s, clock_rate);
67 if (!IS_ERR(i2s->clk_sync_input)) {
69 * Other I/O modules in AHUB can use i2s bclk as reference
73 err = clk_set_rate(i2s->clk_sync_input, clock_rate);
89 struct tegra210_i2s *i2s = dev_get_drvdata(dev);
107 regmap_read(i2s->regmap, cif_reg, &cif_ctrl);
108 regmap_read(i2s->regmap, stream_reg, &stream_ctrl);
109 regmap_read(i2s->regmap, TEGRA210_I2S_CTRL, &i2s_ctrl);
112 regmap_update_bits(i2s->regmap, reset_reg, reset_mask, reset_en);
114 err = regmap_read_poll_timeout(i2s->regmap, reset_reg, val,
124 regmap_write(i2s->regmap, cif_reg, cif_ctrl);
125 regmap_write(i2s->regmap, stream_reg, stream_ctrl);
126 regmap_write(i2s->regmap, TEGRA210_I2S_CTRL, i2s_ctrl);
136 struct tegra210_i2s *i2s = dev_get_drvdata(dev);
155 err = regmap_read_poll_timeout(i2s->regmap, status_reg, val,
169 struct tegra210_i2s *i2s = dev_get_drvdata(dev);
171 regcache_cache_only(i2s->regmap, true);
172 regcache_mark_dirty(i2s->regmap);
174 clk_disable_unprepare(i2s->clk_i2s);
181 struct tegra210_i2s *i2s = dev_get_drvdata(dev);
184 err = clk_prepare_enable(i2s->clk_i2s);
190 regcache_cache_only(i2s->regmap, false);
191 regcache_sync(i2s->regmap);
196 static void tegra210_i2s_set_data_offset(struct tegra210_i2s *i2s,
200 regmap_update_bits(i2s->regmap, TEGRA210_I2S_TX_CTRL,
205 regmap_update_bits(i2s->regmap, TEGRA210_I2S_RX_CTRL,
213 struct tegra210_i2s *i2s = snd_soc_dai_get_drvdata(dai);
233 tegra210_i2s_set_data_offset(i2s, 1);
238 tegra210_i2s_set_data_offset(i2s, 0);
244 tegra210_i2s_set_data_offset(i2s, 1);
257 tegra210_i2s_set_data_offset(i2s, 0);
283 regmap_update_bits(i2s->regmap, TEGRA210_I2S_CTRL, mask, val);
285 i2s->dai_fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
294 struct tegra210_i2s *i2s = snd_soc_dai_get_drvdata(dai);
297 i2s->tx_mask = (tx_mask > DEFAULT_I2S_SLOT_MASK) ?
299 i2s->rx_mask = (rx_mask > DEFAULT_I2S_SLOT_MASK) ?
309 struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
311 ucontrol->value.integer.value[0] = i2s->loopback;
320 struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
323 if (value == i2s->loopback)
326 i2s->loopback = value;
328 regmap_update_bits(i2s->regmap, TEGRA210_I2S_CTRL, I2S_CTRL_LPBK_MASK,
329 i2s->loopback << I2S_CTRL_LPBK_SHIFT);
338 struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
340 ucontrol->value.integer.value[0] = i2s->fsync_width;
349 struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
352 if (value == i2s->fsync_width)
355 i2s->fsync_width = value;
365 regmap_update_bits(i2s->regmap, TEGRA210_I2S_CTRL,
367 i2s->fsync_width << I2S_FSYNC_WIDTH_SHIFT);
376 struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
378 ucontrol->value.enumerated.item[0] = i2s->stereo_to_mono[I2S_TX_PATH];
387 struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
390 if (value == i2s->stereo_to_mono[I2S_TX_PATH])
393 i2s->stereo_to_mono[I2S_TX_PATH] = value;
402 struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
404 ucontrol->value.enumerated.item[0] = i2s->mono_to_stereo[I2S_TX_PATH];
413 struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
416 if (value == i2s->mono_to_stereo[I2S_TX_PATH])
419 i2s->mono_to_stereo[I2S_TX_PATH] = value;
428 struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
430 ucontrol->value.enumerated.item[0] = i2s->stereo_to_mono[I2S_RX_PATH];
439 struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
442 if (value == i2s->stereo_to_mono[I2S_RX_PATH])
445 i2s->stereo_to_mono[I2S_RX_PATH] = value;
454 struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
456 ucontrol->value.enumerated.item[0] = i2s->mono_to_stereo[I2S_RX_PATH];
465 struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
468 if (value == i2s->mono_to_stereo[I2S_RX_PATH])
471 i2s->mono_to_stereo[I2S_RX_PATH] = value;
480 struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
482 ucontrol->value.integer.value[0] = i2s->rx_fifo_th;
491 struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
494 if (value == i2s->rx_fifo_th)
497 i2s->rx_fifo_th = value;
506 struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
508 ucontrol->value.integer.value[0] = i2s->bclk_ratio;
517 struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
520 if (value == i2s->bclk_ratio)
523 i2s->bclk_ratio = value;
531 struct tegra210_i2s *i2s = snd_soc_dai_get_drvdata(dai);
533 i2s->bclk_ratio = ratio;
543 struct tegra210_i2s *i2s = dev_get_drvdata(dev);
547 if (i2s->bclk_ratio)
548 num_bclk *= i2s->bclk_ratio;
550 if (i2s->dai_fmt == SND_SOC_DAIFMT_RIGHT_J)
551 tegra210_i2s_set_data_offset(i2s, num_bclk - sample_size);
563 regmap_read(i2s->regmap, TEGRA210_I2S_CTRL, &val);
579 tegra210_i2s_set_slot_ctrl(i2s->regmap, channels,
580 i2s->tx_mask, i2s->rx_mask);
592 regmap_write(i2s->regmap, TEGRA210_I2S_TIMING,
603 struct tegra210_i2s *i2s = snd_soc_dai_get_drvdata(dai);
644 regmap_update_bits(i2s->regmap, TEGRA210_I2S_CTRL,
661 if (i2s->rx_fifo_th > max_th)
662 i2s->rx_fifo_th = max_th;
664 cif_conf.threshold = i2s->rx_fifo_th;
671 cif_conf.mono_conv = i2s->mono_to_stereo[path];
672 cif_conf.stereo_conv = i2s->stereo_to_mono[path];
674 tegra_set_cif(i2s->regmap, reg, &cif_conf);
878 struct tegra210_i2s *i2s;
882 i2s = devm_kzalloc(dev, sizeof(*i2s), GFP_KERNEL);
883 if (!i2s)
886 i2s->rx_fifo_th = DEFAULT_I2S_RX_FIFO_THRESHOLD;
887 i2s->tx_mask = DEFAULT_I2S_SLOT_MASK;
888 i2s->rx_mask = DEFAULT_I2S_SLOT_MASK;
889 i2s->loopback = false;
891 dev_set_drvdata(dev, i2s);
893 i2s->clk_i2s = devm_clk_get(dev, "i2s");
894 if (IS_ERR(i2s->clk_i2s)) {
896 return PTR_ERR(i2s->clk_i2s);
904 i2s->clk_sync_input = devm_clk_get(dev, "sync_input");
905 if (IS_ERR(i2s->clk_sync_input))
912 i2s->regmap = devm_regmap_init_mmio(dev, regs,
914 if (IS_ERR(i2s->regmap)) {
916 return PTR_ERR(i2s->regmap);
919 regcache_cache_only(i2s->regmap, true);
947 { .compatible = "nvidia,tegra210-i2s" },
954 .name = "tegra210-i2s",