Lines Matching defs:i2s
35 #define DRV_NAME "tegra20-i2s"
39 struct tegra20_i2s *i2s = dev_get_drvdata(dev);
41 regcache_cache_only(i2s->regmap, true);
43 clk_disable_unprepare(i2s->clk_i2s);
50 struct tegra20_i2s *i2s = dev_get_drvdata(dev);
53 ret = reset_control_assert(i2s->reset);
57 ret = clk_prepare_enable(i2s->clk_i2s);
65 ret = reset_control_deassert(i2s->reset);
69 regcache_cache_only(i2s->regmap, false);
70 regcache_mark_dirty(i2s->regmap);
72 ret = regcache_sync(i2s->regmap);
79 clk_disable_unprepare(i2s->clk_i2s);
87 struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai);
135 regmap_update_bits(i2s->regmap, TEGRA20_I2S_CTRL, mask, val);
145 struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai);
170 regmap_update_bits(i2s->regmap, TEGRA20_I2S_CTRL, mask, val);
177 ret = clk_set_rate(i2s->clk_i2s, i2sclock);
191 regmap_write(i2s->regmap, TEGRA20_I2S_TIMING, val);
193 regmap_write(i2s->regmap, TEGRA20_I2S_FIFO_SCR,
200 static void tegra20_i2s_start_playback(struct tegra20_i2s *i2s)
202 regmap_update_bits(i2s->regmap, TEGRA20_I2S_CTRL,
207 static void tegra20_i2s_stop_playback(struct tegra20_i2s *i2s)
209 regmap_update_bits(i2s->regmap, TEGRA20_I2S_CTRL,
213 static void tegra20_i2s_start_capture(struct tegra20_i2s *i2s)
215 regmap_update_bits(i2s->regmap, TEGRA20_I2S_CTRL,
220 static void tegra20_i2s_stop_capture(struct tegra20_i2s *i2s)
222 regmap_update_bits(i2s->regmap, TEGRA20_I2S_CTRL,
229 struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai);
236 tegra20_i2s_start_playback(i2s);
238 tegra20_i2s_start_capture(i2s);
244 tegra20_i2s_stop_playback(i2s);
246 tegra20_i2s_stop_capture(i2s);
257 struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai);
259 snd_soc_dai_init_dma_data(dai, &i2s->playback_dma_data,
260 &i2s->capture_dma_data);
274 struct tegra20_i2s *i2s = dev_get_drvdata(dai->dev);
275 struct clk *parent = clk_get_parent(i2s->clk_i2s);
401 struct tegra20_i2s *i2s;
406 i2s = devm_kzalloc(&pdev->dev, sizeof(struct tegra20_i2s), GFP_KERNEL);
407 if (!i2s) {
411 dev_set_drvdata(&pdev->dev, i2s);
413 i2s->dai = tegra20_i2s_dai_template;
414 i2s->dai.name = dev_name(&pdev->dev);
416 i2s->reset = devm_reset_control_get_exclusive(&pdev->dev, "i2s");
417 if (IS_ERR(i2s->reset)) {
418 dev_err(&pdev->dev, "Can't retrieve i2s reset\n");
419 return PTR_ERR(i2s->reset);
422 i2s->clk_i2s = devm_clk_get(&pdev->dev, NULL);
423 if (IS_ERR(i2s->clk_i2s)) {
424 dev_err(&pdev->dev, "Can't retrieve i2s clock\n");
425 ret = PTR_ERR(i2s->clk_i2s);
435 i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
437 if (IS_ERR(i2s->regmap)) {
439 ret = PTR_ERR(i2s->regmap);
443 i2s->capture_dma_data.addr = mem->start + TEGRA20_I2S_FIFO2;
444 i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
445 i2s->capture_dma_data.maxburst = 4;
447 i2s->playback_dma_data.addr = mem->start + TEGRA20_I2S_FIFO1;
448 i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
449 i2s->playback_dma_data.maxburst = 4;
454 &i2s->dai, 1);
485 { .compatible = "nvidia,tegra20-i2s", },