Lines Matching refs:ac97
33 #define DRV_NAME "tegra20-ac97"
37 static void tegra20_ac97_codec_reset(struct snd_ac97 *ac97)
59 static void tegra20_ac97_codec_warm_reset(struct snd_ac97 *ac97)
142 static inline void tegra20_ac97_start_playback(struct tegra20_ac97 *ac97)
144 regmap_update_bits(ac97->regmap, TEGRA20_AC97_FIFO1_SCR,
148 regmap_update_bits(ac97->regmap, TEGRA20_AC97_CTRL,
155 static inline void tegra20_ac97_stop_playback(struct tegra20_ac97 *ac97)
157 regmap_update_bits(ac97->regmap, TEGRA20_AC97_FIFO1_SCR,
160 regmap_update_bits(ac97->regmap, TEGRA20_AC97_CTRL,
164 static inline void tegra20_ac97_start_capture(struct tegra20_ac97 *ac97)
166 regmap_update_bits(ac97->regmap, TEGRA20_AC97_FIFO1_SCR,
171 static inline void tegra20_ac97_stop_capture(struct tegra20_ac97 *ac97)
173 regmap_update_bits(ac97->regmap, TEGRA20_AC97_FIFO1_SCR,
180 struct tegra20_ac97 *ac97 = snd_soc_dai_get_drvdata(dai);
187 tegra20_ac97_start_playback(ac97);
189 tegra20_ac97_start_capture(ac97);
195 tegra20_ac97_stop_playback(ac97);
197 tegra20_ac97_stop_capture(ac97);
208 struct tegra20_ac97 *ac97 = snd_soc_dai_get_drvdata(dai);
210 snd_soc_dai_init_dma_data(dai, &ac97->playback_dma_data,
211 &ac97->capture_dma_data);
222 .name = "tegra-ac97-pcm",
304 struct tegra20_ac97 *ac97;
309 ac97 = devm_kzalloc(&pdev->dev, sizeof(struct tegra20_ac97),
311 if (!ac97) {
315 dev_set_drvdata(&pdev->dev, ac97);
317 ac97->reset = devm_reset_control_get_exclusive(&pdev->dev, "ac97");
318 if (IS_ERR(ac97->reset)) {
319 dev_err(&pdev->dev, "Can't retrieve ac97 reset\n");
320 ret = PTR_ERR(ac97->reset);
324 ac97->clk_ac97 = devm_clk_get(&pdev->dev, NULL);
325 if (IS_ERR(ac97->clk_ac97)) {
326 dev_err(&pdev->dev, "Can't retrieve ac97 clock\n");
327 ret = PTR_ERR(ac97->clk_ac97);
337 ac97->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
339 if (IS_ERR(ac97->regmap)) {
341 ret = PTR_ERR(ac97->regmap);
345 ac97->reset_gpio = of_get_named_gpio(pdev->dev.of_node,
347 if (gpio_is_valid(ac97->reset_gpio)) {
348 ret = devm_gpio_request_one(&pdev->dev, ac97->reset_gpio,
360 ac97->sync_gpio = of_get_named_gpio(pdev->dev.of_node,
362 if (!gpio_is_valid(ac97->sync_gpio)) {
368 ac97->capture_dma_data.addr = mem->start + TEGRA20_AC97_FIFO_RX1;
369 ac97->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
370 ac97->capture_dma_data.maxburst = 4;
372 ac97->playback_dma_data.addr = mem->start + TEGRA20_AC97_FIFO_TX1;
373 ac97->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
374 ac97->playback_dma_data.maxburst = 4;
376 ret = reset_control_assert(ac97->reset);
382 ret = clk_prepare_enable(ac97->clk_ac97);
390 ret = reset_control_deassert(ac97->reset);
417 workdata = ac97;
424 clk_disable_unprepare(ac97->clk_ac97);
433 struct tegra20_ac97 *ac97 = dev_get_drvdata(&pdev->dev);
438 clk_disable_unprepare(ac97->clk_ac97);
444 { .compatible = "nvidia,tegra20-ac97", },