Lines Matching refs:asrc
71 static void tegra186_asrc_lock_stream(struct tegra186_asrc *asrc,
74 regmap_write(asrc->regmap,
82 struct tegra186_asrc *asrc = dev_get_drvdata(dev);
84 regcache_cache_only(asrc->regmap, true);
85 regcache_mark_dirty(asrc->regmap);
92 struct tegra186_asrc *asrc = dev_get_drvdata(dev);
95 regcache_cache_only(asrc->regmap, false);
102 regmap_write(asrc->regmap, TEGRA186_ASRC_GLOBAL_SCRATCH_ADDR,
104 regmap_write(asrc->regmap, TEGRA186_ASRC_GLOBAL_ENB,
107 regcache_sync(asrc->regmap);
110 if (asrc->lane[id].ratio_source !=
114 regmap_write(asrc->regmap,
117 asrc->lane[id].int_part);
119 regmap_write(asrc->regmap,
122 asrc->lane[id].frac_part);
124 tegra186_asrc_lock_stream(asrc, id);
130 static int tegra186_asrc_set_audio_cif(struct tegra186_asrc *asrc,
158 tegra_set_cif(asrc->regmap, reg, &cif_conf);
168 struct tegra186_asrc *asrc = snd_soc_dai_get_drvdata(dai);
172 regmap_write(asrc->regmap,
174 asrc->lane[id].input_thresh);
176 ret = tegra186_asrc_set_audio_cif(asrc, params,
191 struct tegra186_asrc *asrc = snd_soc_dai_get_drvdata(dai);
195 regmap_write(asrc->regmap,
197 asrc->lane[id].output_thresh);
199 ret = tegra186_asrc_set_audio_cif(asrc, params,
207 if (asrc->lane[id].hwcomp_disable) {
208 regmap_update_bits(asrc->regmap,
213 regmap_update_bits(asrc->regmap,
218 regmap_write(asrc->regmap,
224 regmap_update_bits(asrc->regmap,
226 1, asrc->lane[id].ratio_source);
228 if (asrc->lane[id].ratio_source == TEGRA186_ASRC_RATIO_SOURCE_SW) {
229 regmap_write(asrc->regmap,
231 asrc->lane[id].int_part);
232 regmap_write(asrc->regmap,
234 asrc->lane[id].frac_part);
235 tegra186_asrc_lock_stream(asrc, id);
247 struct tegra186_asrc *asrc = snd_soc_component_get_drvdata(cmpnt);
250 ucontrol->value.enumerated.item[0] = asrc->lane[id].ratio_source;
261 struct tegra186_asrc *asrc = snd_soc_component_get_drvdata(cmpnt);
265 asrc->lane[id].ratio_source = ucontrol->value.enumerated.item[0];
267 regmap_update_bits_check(asrc->regmap, asrc_private->reg,
269 asrc->lane[id].ratio_source,
281 struct tegra186_asrc *asrc = snd_soc_component_get_drvdata(cmpnt);
284 regmap_read(asrc->regmap,
286 &asrc->lane[id].int_part);
288 ucontrol->value.integer.value[0] = asrc->lane[id].int_part;
299 struct tegra186_asrc *asrc = snd_soc_component_get_drvdata(cmpnt);
303 if (asrc->lane[id].ratio_source == TEGRA186_ASRC_RATIO_SOURCE_ARAD) {
310 asrc->lane[id].int_part = ucontrol->value.integer.value[0];
312 regmap_update_bits_check(asrc->regmap,
316 asrc->lane[id].int_part, &change);
318 tegra186_asrc_lock_stream(asrc, id);
329 struct tegra186_asrc *asrc = snd_soc_component_get_drvdata(cmpnt);
332 regmap_read(asrc->regmap,
334 &asrc->lane[id].frac_part);
336 ucontrol->value.integer.value[0] = asrc->lane[id].frac_part;
347 struct tegra186_asrc *asrc = snd_soc_component_get_drvdata(cmpnt);
351 if (asrc->lane[id].ratio_source == TEGRA186_ASRC_RATIO_SOURCE_ARAD) {
358 asrc->lane[id].frac_part = ucontrol->value.integer.value[0];
360 regmap_update_bits_check(asrc->regmap,
364 asrc->lane[id].frac_part, &change);
366 tegra186_asrc_lock_stream(asrc, id);
377 struct tegra186_asrc *asrc = snd_soc_component_get_drvdata(cmpnt);
380 ucontrol->value.integer.value[0] = asrc->lane[id].hwcomp_disable;
391 struct tegra186_asrc *asrc = snd_soc_component_get_drvdata(cmpnt);
395 if (value == asrc->lane[id].hwcomp_disable)
398 asrc->lane[id].hwcomp_disable = value;
409 struct tegra186_asrc *asrc = snd_soc_component_get_drvdata(cmpnt);
412 ucontrol->value.integer.value[0] = (asrc->lane[id].input_thresh & 0x3);
423 struct tegra186_asrc *asrc = snd_soc_component_get_drvdata(cmpnt);
425 int value = (asrc->lane[id].input_thresh & ~(0x3)) |
428 if (value == asrc->lane[id].input_thresh)
431 asrc->lane[id].input_thresh = value;
442 struct tegra186_asrc *asrc = snd_soc_component_get_drvdata(cmpnt);
445 ucontrol->value.integer.value[0] = (asrc->lane[id].output_thresh & 0x3);
456 struct tegra186_asrc *asrc = snd_soc_component_get_drvdata(cmpnt);
458 int value = (asrc->lane[id].output_thresh & ~(0x3)) |
461 if (value == asrc->lane[id].output_thresh)
464 asrc->lane[id].output_thresh = value;
473 struct tegra186_asrc *asrc = dev_get_drvdata(cmpnt->dev);
477 regmap_write(asrc->regmap,
959 { .compatible = "nvidia,tegra186-asrc" },
967 struct tegra186_asrc *asrc;
972 asrc = devm_kzalloc(dev, sizeof(*asrc), GFP_KERNEL);
973 if (!asrc)
976 dev_set_drvdata(dev, asrc);
982 asrc->regmap = devm_regmap_init_mmio(dev, regs,
984 if (IS_ERR(asrc->regmap)) {
986 return PTR_ERR(asrc->regmap);
989 regcache_cache_only(asrc->regmap, true);
991 regmap_write(asrc->regmap, TEGRA186_ASRC_GLOBAL_CFG,
996 asrc->lane[i].ratio_source = TEGRA186_ASRC_RATIO_SOURCE_SW;
997 asrc->lane[i].int_part = 1;
998 asrc->lane[i].frac_part = 0;
999 asrc->lane[i].hwcomp_disable = 0;
1000 asrc->lane[i].input_thresh =
1002 asrc->lane[i].output_thresh =
1033 .name = "tegra186-asrc",