Lines Matching refs:i2s
264 static int stm32_i2s_calc_clk_div(struct stm32_i2s_data *i2s,
282 dev_dbg(&i2s->pdev->dev, "Divider: 2*%d(div)+%d(odd) = %d\n",
288 dev_err(&i2s->pdev->dev, "Wrong divider setting\n");
293 dev_dbg(&i2s->pdev->dev,
297 i2s->div = div;
298 i2s->odd = odd;
299 i2s->divider = divider;
304 static int stm32_i2s_set_clk_div(struct stm32_i2s_data *i2s)
308 cgfr = I2S_CGFR_I2SDIV_SET(i2s->div) | (i2s->odd << I2S_CGFR_ODD_SHIFT);
311 return regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
315 static int stm32_i2s_set_parent_clock(struct stm32_i2s_data *i2s,
318 struct platform_device *pdev = i2s->pdev;
323 parent_clk = i2s->x11kclk;
325 parent_clk = i2s->x8kclk;
327 ret = clk_set_parent(i2s->i2sclk, parent_clk);
339 struct stm32_i2s_data *i2s = mclk->i2s_data;
342 ret = stm32_i2s_calc_clk_div(i2s, *prate, rate);
346 mclk->freq = *prate / i2s->divider;
363 struct stm32_i2s_data *i2s = mclk->i2s_data;
366 ret = stm32_i2s_calc_clk_div(i2s, parent_rate, rate);
370 ret = stm32_i2s_set_clk_div(i2s);
382 struct stm32_i2s_data *i2s = mclk->i2s_data;
384 dev_dbg(&i2s->pdev->dev, "Enable master clock\n");
386 return regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
393 struct stm32_i2s_data *i2s = mclk->i2s_data;
395 dev_dbg(&i2s->pdev->dev, "Disable master clock\n");
397 regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG, I2S_CGFR_MCKOE, 0);
408 static int stm32_i2s_add_mclk_provider(struct stm32_i2s_data *i2s)
412 struct device *dev = &i2s->pdev->dev;
413 const char *pname = __clk_get_name(i2s->i2sclk);
438 mclk->i2s_data = i2s;
442 ret = devm_clk_hw_register(&i2s->pdev->dev, hw);
447 i2s->i2smclk = hw->clk;
455 struct stm32_i2s_data *i2s = (struct stm32_i2s_data *)devid;
456 struct platform_device *pdev = i2s->pdev;
461 regmap_read(i2s->regmap, STM32_I2S_SR_REG, &sr);
462 regmap_read(i2s->regmap, STM32_I2S_IER_REG, &ier);
471 regmap_write_bits(i2s->regmap, STM32_I2S_IFCR_REG,
487 spin_lock(&i2s->irq_lock);
488 if (err && i2s->substream)
489 snd_pcm_stop_xrun(i2s->substream);
490 spin_unlock(&i2s->irq_lock);
544 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
598 i2s->ms_flg = I2S_MS_SLAVE;
601 i2s->ms_flg = I2S_MS_MASTER;
609 i2s->fmt = fmt;
610 return regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
617 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
621 freq, STM32_I2S_IS_MASTER(i2s) ? "master" : "slave",
625 if (dir == SND_SOC_CLOCK_OUT && STM32_I2S_IS_MASTER(i2s)) {
626 if (!i2s->i2smclk) {
634 if (i2s->mclk_rate) {
635 clk_rate_exclusive_put(i2s->i2smclk);
636 i2s->mclk_rate = 0;
638 return regmap_update_bits(i2s->regmap,
643 ret = stm32_i2s_set_parent_clock(i2s, freq);
646 ret = clk_set_rate_exclusive(i2s->i2smclk, freq);
651 ret = regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
654 i2s->mclk_rate = freq;
663 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
671 clk_set_parent(i2s->i2sclk, i2s->x11kclk);
673 clk_set_parent(i2s->i2sclk, i2s->x8kclk);
674 i2s_clock_rate = clk_get_rate(i2s->i2sclk);
678 * i2s mode : mclk_ratio = 256
682 * i2s mode : div = i2s_clk / (mclk_ratio * ws)
685 * i2s mode : div = i2s_clk / (nb_bits x ws)
688 if (i2s->mclk_rate) {
689 ret = stm32_i2s_calc_clk_div(i2s, i2s_clock_rate,
690 i2s->mclk_rate);
695 if ((i2s->fmt & SND_SOC_DAIFMT_FORMAT_MASK) ==
700 ret = regmap_read(i2s->regmap, STM32_I2S_CGFR_REG, &cgfr);
705 ret = stm32_i2s_calc_clk_div(i2s, i2s_clock_rate,
711 ret = stm32_i2s_set_clk_div(i2s);
716 return regmap_update_bits(i2s->regmap, STM32_I2S_CFG2_REG,
724 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
745 if (STM32_I2S_IS_SLAVE(i2s)) {
756 ret = regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
764 return regmap_update_bits(i2s->regmap, STM32_I2S_CFG1_REG,
771 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
775 spin_lock_irqsave(&i2s->irq_lock, flags);
776 i2s->substream = substream;
777 spin_unlock_irqrestore(&i2s->irq_lock, flags);
779 if ((i2s->fmt & SND_SOC_DAIFMT_FORMAT_MASK) != SND_SOC_DAIFMT_DSP_A)
783 ret = clk_prepare_enable(i2s->i2sclk);
789 return regmap_write_bits(i2s->regmap, STM32_I2S_IFCR_REG,
797 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
806 if (STM32_I2S_IS_MASTER(i2s))
815 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
824 /* Enable i2s */
829 regmap_update_bits(i2s->regmap, STM32_I2S_CFG1_REG,
832 ret = regmap_update_bits(i2s->regmap, STM32_I2S_CR1_REG,
839 ret = regmap_write_bits(i2s->regmap, STM32_I2S_CR1_REG,
846 regmap_write_bits(i2s->regmap, STM32_I2S_IFCR_REG,
849 spin_lock(&i2s->lock_fd);
850 i2s->refcount++;
856 if (STM32_I2S_IS_MASTER(i2s) && i2s->refcount == 1)
858 regmap_write(i2s->regmap,
861 spin_unlock(&i2s->lock_fd);
863 if (STM32_I2S_IS_SLAVE(i2s))
866 regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG, ier, ier);
875 regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG,
879 regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG,
883 spin_lock(&i2s->lock_fd);
884 i2s->refcount--;
885 if (i2s->refcount) {
886 spin_unlock(&i2s->lock_fd);
890 ret = regmap_update_bits(i2s->regmap, STM32_I2S_CR1_REG,
894 spin_unlock(&i2s->lock_fd);
897 spin_unlock(&i2s->lock_fd);
900 regmap_update_bits(i2s->regmap, STM32_I2S_CFG1_REG,
913 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
916 clk_disable_unprepare(i2s->i2sclk);
918 spin_lock_irqsave(&i2s->irq_lock, flags);
919 i2s->substream = NULL;
920 spin_unlock_irqrestore(&i2s->irq_lock, flags);
925 struct stm32_i2s_data *i2s = dev_get_drvdata(cpu_dai->dev);
926 struct snd_dmaengine_dai_dma_data *dma_data_tx = &i2s->dma_data_tx;
927 struct snd_dmaengine_dai_dma_data *dma_data_rx = &i2s->dma_data_rx;
931 dma_data_tx->addr = (dma_addr_t)(i2s->phys_addr) + STM32_I2S_TXDR_REG;
934 dma_data_rx->addr = (dma_addr_t)(i2s->phys_addr) + STM32_I2S_RXDR_REG;
981 .name = "stm32-i2s",
997 struct stm32_i2s_data *i2s)
1010 i2s->dai_drv = dai_ptr;
1017 .compatible = "st,stm32h7-i2s",
1024 struct stm32_i2s_data *i2s)
1037 i2s->regmap_conf = (const struct regmap_config *)of_id->data;
1041 i2s->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1042 if (IS_ERR(i2s->base))
1043 return PTR_ERR(i2s->base);
1045 i2s->phys_addr = res->start;
1048 i2s->pclk = devm_clk_get(&pdev->dev, "pclk");
1049 if (IS_ERR(i2s->pclk))
1050 return dev_err_probe(&pdev->dev, PTR_ERR(i2s->pclk),
1053 i2s->i2sclk = devm_clk_get(&pdev->dev, "i2sclk");
1054 if (IS_ERR(i2s->i2sclk))
1055 return dev_err_probe(&pdev->dev, PTR_ERR(i2s->i2sclk),
1058 i2s->x8kclk = devm_clk_get(&pdev->dev, "x8k");
1059 if (IS_ERR(i2s->x8kclk))
1060 return dev_err_probe(&pdev->dev, PTR_ERR(i2s->x8kclk),
1063 i2s->x11kclk = devm_clk_get(&pdev->dev, "x11k");
1064 if (IS_ERR(i2s->x11kclk))
1065 return dev_err_probe(&pdev->dev, PTR_ERR(i2s->x11kclk),
1070 ret = stm32_i2s_add_mclk_provider(i2s);
1081 dev_name(&pdev->dev), i2s);
1109 struct stm32_i2s_data *i2s;
1113 i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
1114 if (!i2s)
1117 i2s->pdev = pdev;
1118 i2s->ms_flg = I2S_MS_NOT_SET;
1119 spin_lock_init(&i2s->lock_fd);
1120 spin_lock_init(&i2s->irq_lock);
1121 platform_set_drvdata(pdev, i2s);
1123 ret = stm32_i2s_parse_dt(pdev, i2s);
1127 ret = stm32_i2s_dais_init(pdev, i2s);
1131 i2s->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "pclk",
1132 i2s->base, i2s->regmap_conf);
1133 if (IS_ERR(i2s->regmap))
1134 return dev_err_probe(&pdev->dev, PTR_ERR(i2s->regmap),
1142 i2s->dai_drv, 1);
1148 /* Set SPI/I2S in i2s mode */
1149 ret = regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
1154 ret = regmap_read(i2s->regmap, STM32_I2S_IPIDR_REG, &val);
1159 ret = regmap_read(i2s->regmap, STM32_I2S_HWCFGR_REG, &val);
1165 "Device does not support i2s mode\n");
1170 ret = regmap_read(i2s->regmap, STM32_I2S_VERR_REG, &val);
1194 struct stm32_i2s_data *i2s = dev_get_drvdata(dev);
1196 regcache_cache_only(i2s->regmap, true);
1197 regcache_mark_dirty(i2s->regmap);
1204 struct stm32_i2s_data *i2s = dev_get_drvdata(dev);
1206 regcache_cache_only(i2s->regmap, false);
1207 return regcache_sync(i2s->regmap);
1217 .name = "st,stm32-i2s",
1227 MODULE_DESCRIPTION("STM32 Soc i2s Interface");
1229 MODULE_ALIAS("platform:stm32-i2s");