Lines Matching refs:buffer
28 /* Stage 0 IRAM buffer size definition */
36 /* Stage 1 DDR buffer size definition */
58 * For 2-stage DMA transfer, we can allocate 2 buffers: IRAM buffer (always
59 * power-on) and DDR buffer. The source channel will transfer data from IRAM
60 * buffer to the DSP fifo to decoding/encoding, once IRAM buffer is empty by
62 * DDR buffer to IRAM buffer.
64 * Since the DSP fifo is only 512B, IRAM buffer is allocated by 32K, and DDR
65 * buffer is larger to 2M. That means only the IRAM 32k data is transferred
77 /* Stage 0 IRAM buffer */
79 /* Stage 1 DDR buffer */
82 /* DSP play information IRAM buffer */
87 /* Data size copied to IRAM buffer */
91 /* Stage 0 IRAM buffer received data size */
93 /* Stage 1 DDR buffer received data size */
95 /* Stage 1 DDR buffer pointer */
121 /* Update data size copied to IRAM buffer */
173 period_cnt = params->buffer.fragment_size / period;
184 period = params->buffer.fragment_size;
185 period_cnt = params->buffer.fragments;
339 * Allocate the stage 0 IRAM buffer size, including the DMA 0
359 * Allocate the stage 1 DDR buffer size, including the DMA 1 link-list
539 * We usually set fragment size as 32K, and the stage 0 IRAM buffer
541 * IRAM buffer is less than 32K, that means we have some available
542 * spaces for the stage 0 IRAM buffer.
550 * Copy data to the stage 0 IRAM buffer directly if
562 * of the stage 0 IRAM buffer, we should copy one
563 * partial data to the stage 0 IRAM buffer, and copy
564 * the left to the stage 1 DDR buffer.
577 * Copy data to the stage 1 DDR buffer if no spaces for the stage 0 IRAM
578 * buffer.