Lines Matching refs:sdev
28 static void mtl_ipc_host_done(struct snd_sof_dev *sdev)
34 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDR,
39 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDA,
43 static void mtl_ipc_dsp_done(struct snd_sof_dev *sdev)
49 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDA,
53 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXCTL,
58 bool mtl_dsp_check_ipc_irq(struct snd_sof_dev *sdev)
63 if (sdev->dspless_mode_selected)
67 hfintipptr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_HFINTIPPTR) & MTL_HFINTIPPTR_PTR_MASK;
68 irq_status = snd_sof_dsp_read(sdev, HDA_DSP_BAR, hfintipptr + MTL_DSP_IRQSTS);
70 trace_sof_intel_hda_irq_ipc_check(sdev, irq_status);
79 static bool mtl_dsp_check_sdw_irq(struct snd_sof_dev *sdev)
85 hfintipptr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_HFINTIPPTR) & MTL_HFINTIPPTR_PTR_MASK;
86 irq_status = snd_sof_dsp_read(sdev, HDA_DSP_BAR, hfintipptr + MTL_DSP_IRQSTS);
94 int mtl_ipc_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
96 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;
99 if (hda_ipc4_tx_is_busy(sdev)) {
108 sof_mailbox_write(sdev, sdev->host_box.offset, msg_data->data_ptr,
111 snd_sof_dsp_write(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDDY,
113 snd_sof_dsp_write(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDR,
121 void mtl_enable_ipc_interrupts(struct snd_sof_dev *sdev)
123 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
126 if (sdev->dspless_mode_selected)
130 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl,
135 void mtl_disable_ipc_interrupts(struct snd_sof_dev *sdev)
137 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
140 if (sdev->dspless_mode_selected)
144 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl,
148 static void mtl_enable_sdw_irq(struct snd_sof_dev *sdev, bool enable)
155 if (sdev->dspless_mode_selected)
165 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfSNDWIE, mask, val);
168 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfSNDWIE, hipcie,
172 dev_err(sdev->dev, "failed to set SoundWire IPC interrupt %s\n",
176 int mtl_enable_interrupts(struct snd_sof_dev *sdev, bool enable)
185 if (sdev->dspless_mode_selected)
189 hfintipptr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_HFINTIPPTR) & MTL_HFINTIPPTR_PTR_MASK;
198 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, hfintipptr, mask, val);
201 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, hfintipptr, irqinten,
205 dev_err(sdev->dev, "failed to %s Host IPC and/or SOUNDWIRE\n",
217 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfHIPCIE, mask, val);
220 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfHIPCIE, hipcie,
224 dev_err(sdev->dev, "failed to set Host IPC interrupt %s\n",
233 int mtl_dsp_pre_fw_run(struct snd_sof_dev *sdev)
235 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;
243 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_HFDSSCS,
251 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_HFDSSCS, dsphfdsscs,
255 dev_err(sdev->dev, "failed to enable DSP subsystem\n");
260 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_HFPWRCTL,
267 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_HFPWRSTS, dsphfpwrsts,
272 dev_err(sdev->dev, "failed to power up gated DSP domain\n");
276 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_HFPWRCTL,
282 int mtl_dsp_post_fw_run(struct snd_sof_dev *sdev)
286 if (sdev->first_boot) {
287 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;
289 ret = hda_sdw_startup(sdev);
291 dev_err(sdev->dev, "could not startup SoundWire links\n");
300 hda_sdw_int_enable(sdev, true);
304 void mtl_dsp_dump(struct snd_sof_dev *sdev, u32 flags)
312 fwsts = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_ROM_STS);
313 fwlec = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_ROM_ERROR);
314 romdbgsts = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFFLGPXQWY);
315 romdbgerr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFFLGPXQWY_ERROR);
317 dev_err(sdev->dev, "ROM status: %#x, ROM error: %#x\n", fwsts, fwlec);
318 dev_err(sdev->dev, "ROM debug status: %#x, ROM debug error: %#x\n", romdbgsts,
320 romdbgsts = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFFLGPXQWY + 0x8 * 3);
321 dev_printk(level, sdev->dev, "ROM feature bit%s enabled\n",
325 static bool mtl_dsp_primary_core_is_enabled(struct snd_sof_dev *sdev)
329 val = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE);
336 static int mtl_dsp_core_power_up(struct snd_sof_dev *sdev, int core)
343 if (core != SOF_DSP_PRIMARY_CORE || mtl_dsp_primary_core_is_enabled(sdev))
347 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE,
352 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE,
361 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE, dspcxctl,
365 dev_err(sdev->dev, "%s: timeout on MTL_DSP2CXCTL_PRIMARY_CORE read\n",
371 sdev->enabled_cores_mask = BIT(SOF_DSP_PRIMARY_CORE);
372 sdev->dsp_core_ref_count[SOF_DSP_PRIMARY_CORE] = 1;
377 static int mtl_dsp_core_power_down(struct snd_sof_dev *sdev, int core)
383 if (core != SOF_DSP_PRIMARY_CORE || !mtl_dsp_primary_core_is_enabled(sdev))
387 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE,
393 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE, dspcxctl,
398 dev_err(sdev->dev, "failed to power down primary core\n");
402 sdev->enabled_cores_mask = 0;
403 sdev->dsp_core_ref_count[SOF_DSP_PRIMARY_CORE] = 0;
408 int mtl_power_down_dsp(struct snd_sof_dev *sdev)
414 ret = mtl_dsp_core_power_down(sdev, SOF_DSP_PRIMARY_CORE);
416 dev_err(sdev->dev, "mtl dsp power down error, %d\n", ret);
421 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_HFDSSCS,
429 dsphfdsscs = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_HFDSSCS);
430 return snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_HFDSSCS, dsphfdsscs,
435 int mtl_dsp_cl_init(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot)
437 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
448 snd_sof_dsp_write(sdev, HDA_DSP_BAR, chip->ipc_req, ipc_hdr);
451 ret = mtl_dsp_core_power_up(sdev, SOF_DSP_PRIMARY_CORE);
454 dev_err(sdev->dev, "dsp core 0/1 power up failed\n");
458 dev_dbg(sdev->dev, "Primary core power up successful\n");
461 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, chip->ipc_ack, status,
466 dev_err(sdev->dev, "timeout waiting for purge IPC done\n");
471 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, chip->ipc_ack, chip->ipc_ack_mask,
475 ret = mtl_enable_interrupts(sdev, true);
478 dev_err(sdev->dev, "%s: failed to enable interrupts\n", __func__);
482 mtl_enable_ipc_interrupts(sdev);
493 snd_sof_dsp_dbg_dump(sdev, "MTL DSP init fail", 0);
494 mtl_dsp_core_power_down(sdev, SOF_DSP_PRIMARY_CORE);
501 struct snd_sof_dev *sdev = context;
507 hipcida = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDA);
508 hipctdr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDR);
513 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXCTL,
516 mtl_ipc_dsp_done(sdev);
524 u32 extension = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDDY);
533 if (likely(sdev->fw_state == SOF_FW_BOOT_COMPLETE)) {
534 struct sof_ipc4_msg *data = sdev->ipc->msg.reply_data;
539 spin_lock_irq(&sdev->ipc_lock);
541 snd_sof_ipc_get_reply(sdev);
542 mtl_ipc_host_done(sdev);
543 snd_sof_ipc_reply(sdev, data->primary);
545 spin_unlock_irq(&sdev->ipc_lock);
547 dev_dbg_ratelimited(sdev->dev,
556 sdev->ipc->msg.rx_data = ¬ification_data;
557 snd_sof_ipc_msgs_rx(sdev);
558 sdev->ipc->msg.rx_data = NULL;
560 mtl_ipc_host_done(sdev);
568 dev_dbg_ratelimited(sdev->dev, "nothing to do in IPC IRQ thread\n");
572 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;
575 mtl_ipc_send_msg(sdev, hdev->delayed_ipc_tx_msg);
581 int mtl_dsp_ipc_get_mailbox_offset(struct snd_sof_dev *sdev)
586 int mtl_dsp_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id)
591 void mtl_ipc_dump(struct snd_sof_dev *sdev)
595 hipcidr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDR);
596 hipcidd = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDDY);
597 hipcida = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDA);
598 hipctdr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDR);
599 hipctdd = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDDY);
600 hipctda = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDA);
601 hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXCTL);
603 dev_err(sdev->dev,
608 static int mtl_dsp_disable_interrupts(struct snd_sof_dev *sdev)
610 mtl_enable_sdw_irq(sdev, false);
611 mtl_disable_ipc_interrupts(sdev);
612 return mtl_enable_interrupts(sdev, false);
615 u64 mtl_dsp_get_stream_hda_link_position(struct snd_sof_dev *sdev,
622 llp_l = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, MTL_PPLCLLPL(hstream->index));
623 llp_u = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, MTL_PPLCLLPU(hstream->index));
627 static int mtl_dsp_core_get(struct snd_sof_dev *sdev, int core)
629 const struct sof_ipc_pm_ops *pm_ops = sdev->ipc->ops->pm;
632 return mtl_dsp_core_power_up(sdev, SOF_DSP_PRIMARY_CORE);
635 return pm_ops->set_core_state(sdev, core, true);
640 static int mtl_dsp_core_put(struct snd_sof_dev *sdev, int core)
642 const struct sof_ipc_pm_ops *pm_ops = sdev->ipc->ops->pm;
646 ret = pm_ops->set_core_state(sdev, core, false);
652 return mtl_dsp_core_power_down(sdev, SOF_DSP_PRIMARY_CORE);
661 int sof_mtl_ops_init(struct snd_sof_dev *sdev)
698 sdev->private = devm_kzalloc(sdev->dev, sizeof(struct sof_ipc4_fw_data), GFP_KERNEL);
699 if (!sdev->private)
702 ipc4_data = sdev->private;
711 hda_set_dai_drv_ops(sdev, &sof_mtl_ops);