Lines Matching refs:sdev
29 static void hda_ssp_set_cbp_cfp(struct snd_sof_dev *sdev)
31 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
37 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
46 struct hdac_ext_stream *hda_cl_stream_prepare(struct snd_sof_dev *sdev, unsigned int format,
52 struct pci_dev *pci = to_pci_dev(sdev->dev);
55 hext_stream = hda_dsp_stream_get(sdev, direction, 0);
58 dev_err(sdev->dev, "error: no stream available\n");
67 dev_err(sdev->dev, "error: memory alloc failed: %d\n", ret);
76 ret = hda_dsp_iccmax_stream_hw_params(sdev, hext_stream, dmab, NULL);
78 dev_err(sdev->dev, "error: iccmax stream prepare failed: %d\n", ret);
82 ret = hda_dsp_stream_hw_params(sdev, hext_stream, dmab, NULL);
84 dev_err(sdev->dev, "error: hdac prepare failed: %d\n", ret);
87 hda_dsp_stream_spib_config(sdev, hext_stream, HDA_DSP_SPIB_ENABLE, size);
95 hda_dsp_stream_put(sdev, direction, hstream->stream_tag);
104 int cl_dsp_init(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot)
106 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
115 ret = hda_dsp_core_power_up(sdev, chip->host_managed_cores_mask);
118 dev_err(sdev->dev, "error: dsp core 0/1 power up failed\n");
122 hda_ssp_set_cbp_cfp(sdev);
129 snd_sof_dsp_write(sdev, HDA_DSP_BAR, chip->ipc_req, ipc_hdr);
132 ret = hda_dsp_core_run(sdev, chip->init_core_mask);
135 dev_err(sdev->dev,
142 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
151 dev_err(sdev->dev,
158 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR,
164 ret = hda_dsp_core_reset_power_down(sdev, chip->host_managed_cores_mask &
168 dev_err(sdev->dev,
174 hda_dsp_ipc_int_enable(sdev);
186 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
194 sdev->enabled_cores_mask |= chip->init_core_mask;
195 mask = sdev->enabled_cores_mask;
197 sdev->dsp_core_ref_count[j]++;
202 dev_err(sdev->dev,
215 snd_sof_dsp_dbg_dump(sdev, dump_msg, flags);
216 hda_dsp_core_reset_power_down(sdev, chip->host_managed_cores_mask);
222 static int cl_trigger(struct snd_sof_dev *sdev,
231 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,
235 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
245 return hda_dsp_stream_trigger(sdev, hext_stream, cmd);
249 int hda_cl_cleanup(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab,
257 ret = hda_dsp_stream_spib_config(sdev, hext_stream, HDA_DSP_SPIB_DISABLE, 0);
259 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset,
262 hda_dsp_stream_put(sdev, hstream->direction, hstream->stream_tag);
267 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
269 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
272 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, sd_offset, 0);
281 int hda_cl_copy_fw(struct snd_sof_dev *sdev, struct hdac_ext_stream *hext_stream)
283 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
288 ret = cl_trigger(sdev, hext_stream, SNDRV_PCM_TRIGGER_START);
290 dev_err(sdev->dev, "error: DMA trigger start failed\n");
294 status = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
306 dev_err(sdev->dev,
311 ret = cl_trigger(sdev, hext_stream, SNDRV_PCM_TRIGGER_STOP);
313 dev_err(sdev->dev, "error: DMA trigger stop failed\n");
321 int hda_dsp_cl_boot_firmware_iccmax(struct snd_sof_dev *sdev)
329 original_gb = snd_sof_dsp_read8(sdev, HDA_DSP_HDA_BAR, HDA_VS_INTEL_LTRP) &
336 iccmax_stream = hda_cl_stream_prepare(sdev, HDA_CL_STREAM_FORMAT, PAGE_SIZE,
339 dev_err(sdev->dev, "error: dma prepare for ICCMAX stream failed\n");
343 ret = hda_dsp_cl_boot_firmware(sdev);
349 ret1 = hda_cl_cleanup(sdev, &dmab_bdl, iccmax_stream);
351 dev_err(sdev->dev, "error: ICCMAX stream cleanup failed\n");
359 snd_sof_dsp_update8(sdev, HDA_DSP_HDA_BAR, HDA_VS_INTEL_LTRP,
365 static int hda_dsp_boot_imr(struct snd_sof_dev *sdev)
370 chip_info = get_chip_info(sdev->pdata);
372 ret = chip_info->cl_init(sdev, 0, true);
377 hda_sdw_process_wakeen(sdev);
382 int hda_dsp_cl_boot_firmware(struct snd_sof_dev *sdev)
384 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
385 struct snd_sof_pdata *plat_data = sdev->pdata;
393 if (hda->imrboot_supported && !sdev->first_boot && !hda->skip_imr_boot) {
394 dev_dbg(sdev->dev, "IMR restore supported, booting from IMR directly\n");
396 ret = hda_dsp_boot_imr(sdev);
402 dev_warn(sdev->dev, "IMR restore failed, trying to cold boot\n");
409 if (sdev->basefw.fw->size <= sdev->basefw.payload_offset) {
410 dev_err(sdev->dev, "error: firmware size must be greater than firmware offset\n");
414 stripped_firmware.data = sdev->basefw.fw->data + sdev->basefw.payload_offset;
415 stripped_firmware.size = sdev->basefw.fw->size - sdev->basefw.payload_offset;
418 init_waitqueue_head(&sdev->boot_wait);
421 hext_stream = hda_cl_stream_prepare(sdev, HDA_CL_STREAM_FORMAT,
425 dev_err(sdev->dev, "error: dma prepare for fw loading failed\n");
434 dev_dbg(sdev->dev,
439 ret = chip_info->cl_init(sdev, hext_stream->hstream.stream_tag, false);
449 dev_err(sdev->dev, "error: dsp init failed after %d attempts with err: %d\n",
469 if (!sdev->first_boot)
470 hda_sdw_process_wakeen(sdev);
480 ret = hda_cl_copy_fw(sdev, hext_stream);
482 dev_dbg(sdev->dev, "Firmware download successful, booting...\n");
485 snd_sof_dsp_dbg_dump(sdev, "Firmware download failed",
496 ret1 = hda_cl_cleanup(sdev, &dmab, hext_stream);
498 dev_err(sdev->dev, "error: Code loader DSP cleanup failed\n");
513 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR,
519 int hda_dsp_ipc4_load_library(struct snd_sof_dev *sdev,
522 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
538 hext_stream = hda_cl_stream_prepare(sdev, HDA_CL_STREAM_FORMAT,
542 dev_err(sdev->dev, "%s: DMA prepare failed\n", __func__);
554 ret = cl_trigger(sdev, hext_stream, SNDRV_PCM_TRIGGER_START);
556 dev_err(sdev->dev, "%s: DMA trigger start failed\n", __func__);
560 ret = sof_ipc_tx_message_no_reply(sdev->ipc, &msg, 0);
562 ret1 = cl_trigger(sdev, hext_stream, SNDRV_PCM_TRIGGER_STOP);
564 dev_err(sdev->dev, "%s: DMA trigger stop failed\n", __func__);
571 ret1 = hda_cl_cleanup(sdev, &dmab, hext_stream);
573 dev_err(sdev->dev, "%s: Code loader DSP cleanup failed\n", __func__);
584 int hda_dsp_pre_fw_run(struct snd_sof_dev *sdev)
587 return hda_dsp_ctrl_clock_power_gating(sdev, false);
591 int hda_dsp_post_fw_run(struct snd_sof_dev *sdev)
595 if (sdev->first_boot) {
596 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;
598 ret = hda_sdw_startup(sdev);
600 dev_err(sdev->dev,
607 (sdev->fw_ready.flags & SOF_IPC_INFO_D3_PERSISTENT ||
608 sdev->pdata->ipc_type == SOF_INTEL_IPC4))
612 hda_sdw_int_enable(sdev, true);
615 return hda_dsp_ctrl_clock_power_gating(sdev, true);
618 int hda_dsp_ext_man_get_cavs_config_data(struct snd_sof_dev *sdev,
623 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
630 dev_err(sdev->dev, "cavs config data is inconsistent: %d\n", elem_num);
641 dev_dbg(sdev->dev, "FW clock config: %s\n",
649 dev_info(sdev->dev, "unsupported token type: %d\n",