Lines Matching refs:sdev
23 static void hda_dsp_ipc_host_done(struct snd_sof_dev *sdev)
29 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR,
35 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
41 static void hda_dsp_ipc_dsp_done(struct snd_sof_dev *sdev)
47 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR,
53 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
59 int hda_dsp_ipc_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
62 sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data,
64 snd_sof_dsp_write(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCI,
96 int hda_dsp_ipc4_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
98 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;
101 if (hda_ipc4_tx_is_busy(sdev)) {
110 sof_mailbox_write(sdev, sdev->host_box.offset, msg_data->data_ptr,
113 snd_sof_dsp_write(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCIE, msg_data->extension);
114 snd_sof_dsp_write(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCI,
122 void hda_dsp_ipc_get_reply(struct snd_sof_dev *sdev)
124 struct snd_sof_ipc_msg *msg = sdev->msg;
134 dev_warn(sdev->dev, "unexpected ipc interrupt raised!\n");
153 snd_sof_ipc_get_reply(sdev);
160 struct snd_sof_dev *sdev = context;
165 hipcie = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCIE);
166 hipct = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCT);
170 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCCTL,
172 hda_dsp_ipc_dsp_done(sdev);
180 u32 hipcte = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
186 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCCTL,
191 if (likely(sdev->fw_state == SOF_FW_BOOT_COMPLETE)) {
192 struct sof_ipc4_msg *data = sdev->ipc->msg.reply_data;
197 spin_lock_irq(&sdev->ipc_lock);
199 snd_sof_ipc_get_reply(sdev);
200 hda_dsp_ipc_host_done(sdev);
201 snd_sof_ipc_reply(sdev, data->primary);
203 spin_unlock_irq(&sdev->ipc_lock);
205 dev_dbg_ratelimited(sdev->dev,
214 sdev->ipc->msg.rx_data = ¬ification_data;
215 snd_sof_ipc_msgs_rx(sdev);
216 sdev->ipc->msg.rx_data = NULL;
219 hda_dsp_ipc_host_done(sdev);
227 dev_dbg_ratelimited(sdev->dev, "nothing to do in IPC IRQ thread\n");
230 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;
233 hda_dsp_ipc4_send_msg(sdev, hdev->delayed_ipc_tx_msg);
242 struct snd_sof_dev *sdev = context;
252 hipcie = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
254 hipct = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCT);
255 hipci = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCI);
256 hipcte = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCTE);
263 trace_sof_intel_ipc_firmware_response(sdev, msg, msg_ext);
266 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
280 if (likely(sdev->fw_state == SOF_FW_BOOT_COMPLETE)) {
281 spin_lock_irq(&sdev->ipc_lock);
284 hda_dsp_ipc_get_reply(sdev);
285 snd_sof_ipc_reply(sdev, msg);
288 hda_dsp_ipc_dsp_done(sdev);
290 spin_unlock_irq(&sdev->ipc_lock);
292 dev_dbg_ratelimited(sdev->dev, "IPC reply before FW_READY: %#x\n",
304 trace_sof_intel_ipc_firmware_initiated(sdev, msg, msg_ext);
307 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
313 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
324 if (sdev->fw_state == SOF_FW_BOOT_IN_PROGRESS &&
328 snd_sof_dsp_panic(sdev, HDA_DSP_PANIC_OFFSET(msg_ext),
332 snd_sof_ipc_msgs_rx(sdev);
335 hda_dsp_ipc_host_done(sdev);
344 dev_dbg_ratelimited(sdev->dev,
352 bool hda_dsp_check_ipc_irq(struct snd_sof_dev *sdev)
354 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
358 if (sdev->dspless_mode_selected)
362 irq_status = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIS);
363 trace_sof_intel_hda_irq_ipc_check(sdev, irq_status);
384 int hda_dsp_ipc_get_mailbox_offset(struct snd_sof_dev *sdev)
389 int hda_dsp_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id)
394 int hda_ipc_msg_data(struct snd_sof_dev *sdev,
398 if (!sps || !sdev->stream_box.size) {
399 sof_mailbox_read(sdev, sdev->dsp_box.offset, p, sz);
413 sof_mailbox_read(sdev, hda_stream->sof_intel_stream.posn_offset, p, sz);
419 int hda_set_stream_data_offset(struct snd_sof_dev *sdev,
431 if (posn_offset > sdev->stream_box.size ||
435 hda_stream->sof_intel_stream.posn_offset = sdev->stream_box.offset + posn_offset;
437 dev_dbg(sdev->dev, "pcm: stream dir %d, posn mailbox offset is %zu",