Lines Matching refs:sdev
39 static int hda_dsp_core_reset_enter(struct snd_sof_dev *sdev, unsigned int core_mask)
47 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
52 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
58 dev_err(sdev->dev,
65 adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
69 dev_err(sdev->dev,
78 static int hda_dsp_core_reset_leave(struct snd_sof_dev *sdev, unsigned int core_mask)
85 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
92 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
99 dev_err(sdev->dev,
106 adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
109 dev_err(sdev->dev,
118 int hda_dsp_core_stall_reset(struct snd_sof_dev *sdev, unsigned int core_mask)
121 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
127 return hda_dsp_core_reset_enter(sdev, core_mask);
130 bool hda_dsp_core_is_enabled(struct snd_sof_dev *sdev, unsigned int core_mask)
135 val = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPCS);
149 dev_dbg(sdev->dev, "DSP core(s) enabled? %d : core_mask %x\n",
155 int hda_dsp_core_run(struct snd_sof_dev *sdev, unsigned int core_mask)
160 ret = hda_dsp_core_reset_leave(sdev, core_mask);
165 dev_dbg(sdev->dev, "unstall/run core: core_mask = %x\n", core_mask);
166 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
172 if (!hda_dsp_core_is_enabled(sdev, core_mask)) {
173 hda_dsp_core_stall_reset(sdev, core_mask);
174 dev_err(sdev->dev, "error: DSP start core failed: core_mask %x\n",
186 int hda_dsp_core_power_up(struct snd_sof_dev *sdev, unsigned int core_mask)
188 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
201 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPCS,
207 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
213 dev_err(sdev->dev,
220 adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
224 dev_err(sdev->dev,
233 static int hda_dsp_core_power_down(struct snd_sof_dev *sdev, unsigned int core_mask)
239 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
243 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
249 dev_err(sdev->dev,
256 int hda_dsp_enable_core(struct snd_sof_dev *sdev, unsigned int core_mask)
258 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
266 if (!core_mask || hda_dsp_core_is_enabled(sdev, core_mask))
270 ret = hda_dsp_core_power_up(sdev, core_mask);
272 dev_err(sdev->dev, "error: dsp core power up failed: core_mask %x\n",
277 return hda_dsp_core_run(sdev, core_mask);
280 int hda_dsp_core_reset_power_down(struct snd_sof_dev *sdev,
283 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
295 ret = hda_dsp_core_stall_reset(sdev, core_mask);
297 dev_err(sdev->dev, "error: dsp core reset failed: core_mask %x\n",
303 ret = hda_dsp_core_power_down(sdev, core_mask);
305 dev_err(sdev->dev, "error: dsp core power down fail mask %x: %d\n",
311 if (hda_dsp_core_is_enabled(sdev, core_mask)) {
312 dev_err(sdev->dev, "error: dsp core disable fail mask %x: %d\n",
320 void hda_dsp_ipc_int_enable(struct snd_sof_dev *sdev)
322 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
325 if (sdev->dspless_mode_selected)
329 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl,
334 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC,
338 void hda_dsp_ipc_int_disable(struct snd_sof_dev *sdev)
340 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
343 if (sdev->dspless_mode_selected)
347 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC,
351 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl,
355 static int hda_dsp_wait_d0i3c_done(struct snd_sof_dev *sdev)
358 struct snd_sof_pdata *pdata = sdev->pdata;
362 while (snd_sof_dsp_read8(sdev, HDA_DSP_HDA_BAR, chip->d0i3_offset) &
372 static int hda_dsp_send_pm_gate_ipc(struct snd_sof_dev *sdev, u32 flags)
374 const struct sof_ipc_pm_ops *pm_ops = sof_ipc_get_ops(sdev, pm);
377 return pm_ops->set_pm_gate(sdev, flags);
382 static int hda_dsp_update_d0i3c_register(struct snd_sof_dev *sdev, u8 value)
384 struct snd_sof_pdata *pdata = sdev->pdata;
392 ret = hda_dsp_wait_d0i3c_done(sdev);
394 dev_err(sdev->dev, "CIP timeout before D0I3C update!\n");
399 snd_sof_dsp_update8(sdev, HDA_DSP_HDA_BAR, chip->d0i3_offset,
409 ret = hda_dsp_wait_d0i3c_done(sdev);
411 dev_err(sdev->dev, "CIP timeout after D0I3C update!\n");
415 reg = snd_sof_dsp_read8(sdev, HDA_DSP_HDA_BAR, chip->d0i3_offset);
418 dev_err(sdev->dev, "failed to update D0I3C!\n");
422 trace_sof_intel_D0I3C_updated(sdev, reg);
431 static bool hda_dsp_d0i3_streaming_applicable(struct snd_sof_dev *sdev)
438 list_for_each_entry(spcm, &sdev->pcm_list, list) {
455 static int hda_dsp_set_D0_state(struct snd_sof_dev *sdev,
469 switch (sdev->dsp_power_state.state) {
477 dev_err(sdev->dev, "error: transition from %d to %d not allowed\n",
478 sdev->dsp_power_state.state, target_state->state);
492 if (!sdev->fw_trace_is_supported ||
494 sdev->system_suspend_target != SOF_SUSPEND_NONE)
497 if (hda_dsp_d0i3_streaming_applicable(sdev))
505 ret = hda_dsp_update_d0i3c_register(sdev, value);
514 ret = hda_dsp_send_pm_gate_ipc(sdev, flags);
516 dev_err(sdev->dev,
531 hda_dsp_update_d0i3c_register(sdev, value);
537 static void hda_dsp_state_log(struct snd_sof_dev *sdev)
539 switch (sdev->dsp_power_state.state) {
541 switch (sdev->dsp_power_state.substate) {
543 dev_dbg(sdev->dev, "Current DSP power state: D0I0\n");
546 dev_dbg(sdev->dev, "Current DSP power state: D0I3\n");
549 dev_dbg(sdev->dev, "Unknown DSP D0 substate: %d\n",
550 sdev->dsp_power_state.substate);
555 dev_dbg(sdev->dev, "Current DSP power state: D1\n");
558 dev_dbg(sdev->dev, "Current DSP power state: D2\n");
561 dev_dbg(sdev->dev, "Current DSP power state: D3\n");
564 dev_dbg(sdev->dev, "Unknown DSP power state: %d\n",
565 sdev->dsp_power_state.state);
577 static int hda_dsp_set_power_state(struct snd_sof_dev *sdev,
584 ret = hda_dsp_set_D0_state(sdev, target_state);
588 if (sdev->dsp_power_state.state == SOF_DSP_PM_D0 &&
589 sdev->dsp_power_state.substate == SOF_HDA_DSP_PM_D0I0)
592 dev_err(sdev->dev,
594 sdev->dsp_power_state.state, target_state->state);
597 dev_err(sdev->dev, "error: target state unsupported %d\n",
602 dev_err(sdev->dev,
608 sdev->dsp_power_state = *target_state;
609 hda_dsp_state_log(sdev);
613 int hda_dsp_set_power_state_ipc3(struct snd_sof_dev *sdev,
624 sdev->system_suspend_target == SOF_SUSPEND_S0IX)
625 return hda_dsp_set_power_state(sdev, target_state);
631 if (target_state->state == sdev->dsp_power_state.state &&
632 target_state->substate == sdev->dsp_power_state.substate)
635 return hda_dsp_set_power_state(sdev, target_state);
638 int hda_dsp_set_power_state_ipc4(struct snd_sof_dev *sdev,
642 if (target_state->state == sdev->dsp_power_state.state &&
643 target_state->substate == sdev->dsp_power_state.substate)
646 return hda_dsp_set_power_state(sdev, target_state);
679 static int hda_suspend(struct snd_sof_dev *sdev, bool runtime_suspend)
681 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
683 struct hdac_bus *bus = sof_to_bus(sdev);
693 if (sdev->system_suspend_target > SOF_SUSPEND_S3 ||
694 sdev->fw_state == SOF_FW_CRASHED ||
695 sdev->fw_state == SOF_FW_BOOT_FAILED)
698 ret = chip->disable_interrupts(sdev);
702 hda_codec_jack_wake_enable(sdev, runtime_suspend);
707 if (sdev->dspless_mode_selected)
710 ret = chip->power_down_dsp(sdev);
712 dev_err(sdev->dev, "failed to power down DSP during suspend\n");
718 sdev->dsp_core_ref_count[j] = 0;
721 hda_dsp_ctrl_ppcap_enable(sdev, false);
722 hda_dsp_ctrl_ppcap_int_enable(sdev, false);
726 hda_dsp_ctrl_stop_chip(sdev);
729 snd_sof_pci_update_bits(sdev, PCI_PGCTL,
733 ret = hda_dsp_ctrl_link_reset(sdev, true);
735 dev_err(sdev->dev,
741 hda_codec_i915_display_power(sdev, false);
746 static int hda_resume(struct snd_sof_dev *sdev, bool runtime_resume)
751 hda_codec_i915_display_power(sdev, true);
757 snd_sof_pci_update_bits(sdev, PCI_TCSEL, 0x07, 0);
760 ret = hda_dsp_ctrl_init_chip(sdev);
762 dev_err(sdev->dev,
769 hda_codec_jack_wake_enable(sdev, false);
770 if (sdev->system_suspend_target == SOF_SUSPEND_NONE)
771 hda_codec_jack_check(sdev);
774 if (!sdev->dspless_mode_selected) {
776 hda_dsp_ctrl_ppcap_enable(sdev, true);
777 hda_dsp_ctrl_ppcap_int_enable(sdev, true);
782 hda_codec_i915_display_power(sdev, false);
787 int hda_dsp_resume(struct snd_sof_dev *sdev)
789 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
790 struct hdac_bus *bus = sof_to_bus(sdev);
791 struct pci_dev *pci = to_pci_dev(sdev->dev);
799 if (sdev->dsp_power_state.state == SOF_DSP_PM_D0) {
802 dev_err(sdev->dev,
809 hda_codec_resume_cmd_io(sdev);
812 ret = snd_sof_dsp_set_power_state(sdev, &target_state);
814 dev_err(sdev->dev, "error: setting dsp state %d substate %d\n",
821 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
832 ret = hda_resume(sdev, false);
836 return snd_sof_dsp_set_power_state(sdev, &target_state);
839 int hda_dsp_runtime_resume(struct snd_sof_dev *sdev)
847 ret = hda_resume(sdev, true);
851 return snd_sof_dsp_set_power_state(sdev, &target_state);
854 int hda_dsp_runtime_idle(struct snd_sof_dev *sdev)
856 struct hdac_bus *hbus = sof_to_bus(sdev);
859 dev_dbg(sdev->dev, "some codecs still powered (%08X), not idle\n",
867 int hda_dsp_runtime_suspend(struct snd_sof_dev *sdev)
869 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
875 if (!sdev->dspless_mode_selected) {
881 ret = hda_suspend(sdev, true);
885 return snd_sof_dsp_set_power_state(sdev, &target_state);
888 int hda_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state)
890 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
891 struct hdac_bus *bus = sof_to_bus(sdev);
892 struct pci_dev *pci = to_pci_dev(sdev->dev);
900 if (!sdev->dspless_mode_selected) {
907 ret = snd_sof_dsp_set_power_state(sdev, &target_dsp_state);
909 dev_err(sdev->dev, "error: setting dsp state %d substate %d\n",
917 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, HDA_VS_INTEL_EM2,
921 hda_codec_suspend_cmd_io(sdev);
926 dev_err(sdev->dev,
939 ret = hda_suspend(sdev, false);
945 return snd_sof_dsp_set_power_state(sdev, &target_dsp_state);
948 static unsigned int hda_dsp_check_for_dma_streams(struct snd_sof_dev *sdev)
950 struct hdac_bus *bus = sof_to_bus(sdev);
958 val = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR,
967 static int hda_dsp_s5_quirk(struct snd_sof_dev *sdev)
983 ret = hda_dsp_ctrl_link_reset(sdev, false);
990 ret = hda_dsp_ctrl_link_reset(sdev, true);
997 int hda_dsp_shutdown_dma_flush(struct snd_sof_dev *sdev)
1003 active_streams = hda_dsp_check_for_dma_streams(sdev);
1005 sdev->system_suspend_target = SOF_SUSPEND_S3;
1006 ret = snd_sof_suspend(sdev->dev);
1009 dev_warn(sdev->dev,
1012 ret2 = hda_dsp_s5_quirk(sdev);
1014 dev_err(sdev->dev, "shutdown recovery failed (%d)\n", ret2);
1020 int hda_dsp_shutdown(struct snd_sof_dev *sdev)
1022 sdev->system_suspend_target = SOF_SUSPEND_S3;
1023 return snd_sof_suspend(sdev->dev);
1026 int hda_dsp_set_hw_params_upon_resume(struct snd_sof_dev *sdev)
1031 ret = hda_dsp_dais_suspend(sdev);
1033 dev_warn(sdev->dev, "%s: failure in hda_dsp_dais_suspend\n", __func__);
1044 struct snd_sof_dev *sdev = dev_get_drvdata(bus->dev);
1052 if (!snd_sof_dsp_only_d0i3_compatible_stream_active(sdev))
1057 ret = snd_sof_dsp_set_power_state(sdev, &target_state);
1059 dev_err_ratelimited(sdev->dev,
1064 int hda_dsp_core_get(struct snd_sof_dev *sdev, int core)
1066 const struct sof_ipc_pm_ops *pm_ops = sdev->ipc->ops->pm;
1070 ret = hda_dsp_enable_core(sdev, BIT(core));
1072 dev_err(sdev->dev, "failed to power up core %d with err: %d\n",
1078 if (sdev->fw_state != SOF_FW_BOOT_COMPLETE || core == SOF_DSP_PRIMARY_CORE)
1086 ret = pm_ops->set_core_state(sdev, core, true);
1088 dev_err(sdev->dev, "failed to enable secondary core '%d' failed with %d\n",
1097 ret1 = hda_dsp_core_reset_power_down(sdev, BIT(core));
1099 dev_err(sdev->dev, "failed to power down core: %d with err: %d\n", core, ret1);
1104 int hda_dsp_disable_interrupts(struct snd_sof_dev *sdev)
1106 hda_sdw_int_enable(sdev, false);
1107 hda_dsp_ipc_int_disable(sdev);