Lines Matching refs:sdev
76 static void bdw_host_done(struct snd_sof_dev *sdev);
77 static void bdw_dsp_done(struct snd_sof_dev *sdev);
83 static int bdw_run(struct snd_sof_dev *sdev)
86 snd_sof_dsp_update_bits(sdev, BDW_DSP_BAR, SHIM_HMDC,
91 snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CSR,
98 static int bdw_reset(struct snd_sof_dev *sdev)
101 snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CSR,
109 snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CSR,
116 static int bdw_set_dsp_D0(struct snd_sof_dev *sdev)
122 snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_VDRTCTL2,
127 snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_VDRTCTL0,
131 snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_PMCS,
136 reg = readl(sdev->bar[BDW_PCI_BAR] + PCI_PMCS)
151 snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CSR,
156 snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR,
163 snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CLKCTL,
172 bdw_reset(sdev);
175 snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_VDRTCTL2,
184 snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_VDRTCTL2,
192 snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_VDRTCTL0,
196 snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CSR2,
201 snd_sof_dsp_update_bits(sdev, BDW_DSP_BAR, SHIM_HMDC,
208 snd_sof_dsp_update_bits(sdev, BDW_DSP_BAR, SHIM_IMRX,
210 snd_sof_dsp_update_bits(sdev, BDW_DSP_BAR, SHIM_IMRD,
215 snd_sof_dsp_write(sdev, BDW_DSP_BAR, SHIM_IPCX, 0x0);
216 snd_sof_dsp_write(sdev, BDW_DSP_BAR, SHIM_IPCD, 0x0);
217 snd_sof_dsp_write(sdev, BDW_DSP_BAR, 0x80, 0x6);
218 snd_sof_dsp_write(sdev, BDW_DSP_BAR, 0xe0, 0x300a);
223 static void bdw_get_registers(struct snd_sof_dev *sdev,
228 u32 offset = sdev->dsp_oops_offset;
231 sof_mailbox_read(sdev, offset, xoops, sizeof(*xoops));
237 dev_err(sdev->dev, "invalid header size 0x%x. FW oops is bogus\n",
242 sof_mailbox_read(sdev, offset, panic_info, sizeof(*panic_info));
246 sof_mailbox_read(sdev, offset, stack, stack_words * sizeof(u32));
249 static void bdw_dump(struct snd_sof_dev *sdev, u32 flags)
257 status = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_IPCD);
258 panic = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_IPCX);
259 bdw_get_registers(sdev, &xoops, &panic_info, stack,
261 sof_print_oops_and_stack(sdev, KERN_ERR, status, panic, &xoops,
265 imrx = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_IMRX);
266 imrd = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_IMRD);
267 dev_err(sdev->dev,
271 dev_err(sdev->dev,
275 dev_err(sdev->dev,
279 dev_err(sdev->dev,
291 struct snd_sof_dev *sdev = context;
296 isr = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_ISRX);
305 struct snd_sof_dev *sdev = context;
308 imrx = snd_sof_dsp_read64(sdev, BDW_DSP_BAR, SHIM_IMRX);
309 ipcx = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_IPCX);
315 snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR,
319 spin_lock_irq(&sdev->ipc_lock);
328 snd_sof_ipc_process_reply(sdev, ipcx);
330 bdw_dsp_done(sdev);
332 spin_unlock_irq(&sdev->ipc_lock);
335 ipcd = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_IPCD);
341 snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR,
347 snd_sof_dsp_panic(sdev, BDW_PANIC_OFFSET(ipcx) + MBOX_OFFSET,
350 snd_sof_ipc_msgs_rx(sdev);
353 bdw_host_done(sdev);
363 static int bdw_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
366 sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data,
368 snd_sof_dsp_write(sdev, BDW_DSP_BAR, SHIM_IPCX, SHIM_IPCX_BUSY);
373 static int bdw_get_mailbox_offset(struct snd_sof_dev *sdev)
378 static int bdw_get_window_offset(struct snd_sof_dev *sdev, u32 id)
383 static void bdw_host_done(struct snd_sof_dev *sdev)
386 snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_IPCD,
391 snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_IMRX,
395 static void bdw_dsp_done(struct snd_sof_dev *sdev)
398 snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_IPCX,
402 snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_IMRX,
409 static int bdw_probe(struct snd_sof_dev *sdev)
411 struct snd_sof_pdata *pdata = sdev->pdata;
414 container_of(sdev->dev, struct platform_device, dev);
420 chip = get_chip_info(sdev->pdata);
422 dev_err(sdev->dev, "error: no such device supported\n");
426 sdev->num_cores = chip->cores_num;
435 dev_err(sdev->dev, "error: failed to get LPE base at idx %d\n",
440 dev_dbg(sdev->dev, "LPE PHY base at 0x%x size 0x%x", base, size);
441 sdev->bar[BDW_DSP_BAR] = devm_ioremap(sdev->dev, base, size);
442 if (!sdev->bar[BDW_DSP_BAR]) {
443 dev_err(sdev->dev,
448 dev_dbg(sdev->dev, "LPE VADDR %p\n", sdev->bar[BDW_DSP_BAR]);
451 sdev->mmio_bar = BDW_DSP_BAR;
452 sdev->mailbox_bar = BDW_DSP_BAR;
453 sdev->dsp_oops_offset = MBOX_OFFSET;
462 dev_err(sdev->dev, "error: failed to get PCI base at idx %d\n",
467 dev_dbg(sdev->dev, "PCI base at 0x%x size 0x%x", base, size);
468 sdev->bar[BDW_PCI_BAR] = devm_ioremap(sdev->dev, base, size);
469 if (!sdev->bar[BDW_PCI_BAR]) {
470 dev_err(sdev->dev,
475 dev_dbg(sdev->dev, "PCI VADDR %p\n", sdev->bar[BDW_PCI_BAR]);
478 sdev->ipc_irq = platform_get_irq(pdev, desc->irqindex_host_ipc);
479 if (sdev->ipc_irq < 0)
480 return sdev->ipc_irq;
482 dev_dbg(sdev->dev, "using IRQ %d\n", sdev->ipc_irq);
483 ret = devm_request_threaded_irq(sdev->dev, sdev->ipc_irq,
485 IRQF_SHARED, "AudioDSP", sdev);
487 dev_err(sdev->dev, "error: failed to register IRQ %d\n",
488 sdev->ipc_irq);
493 ret = bdw_set_dsp_D0(sdev);
495 dev_err(sdev->dev, "error: failed to set DSP D0\n");
500 ret = dma_coerce_mask_and_coherent(sdev->dev, DMA_BIT_MASK(31));
502 dev_err(sdev->dev, "error: failed to set DMA mask %d\n", ret);
507 sdev->dsp_box.offset = MBOX_OFFSET;
512 static struct snd_soc_acpi_mach *bdw_machine_select(struct snd_sof_dev *sdev)
514 struct snd_sof_pdata *sof_pdata = sdev->pdata;
520 dev_warn(sdev->dev, "warning: No matching ASoC machine driver found\n");
531 struct snd_sof_dev *sdev)
533 struct snd_sof_pdata *pdata = sdev->pdata;
538 mach_params->platform = dev_name(sdev->dev);