Lines Matching refs:sdev
63 struct snd_sof_dev *sdev = adata->dev;
64 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
67 addr = desc->sram_pte_offset + sdev->debug_box.offset +
70 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_DESC_BASE_ADDR, addr);
71 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_DESC_MAX_NUM_DSCR, ACP_MAX_DESC_CNT);
77 struct snd_sof_dev *sdev = adata->dev;
80 offset = ACP_SCRATCH_REG_0 + sdev->debug_box.offset +
84 snd_sof_dsp_write(sdev, ACP_DSP_BAR, offset, dscr_info->src_addr);
85 snd_sof_dsp_write(sdev, ACP_DSP_BAR, offset + 0x4, dscr_info->dest_addr);
86 snd_sof_dsp_write(sdev, ACP_DSP_BAR, offset + 0x8, dscr_info->tx_cnt.u32_all);
92 struct snd_sof_dev *sdev = adata->dev;
96 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_CNTL_0 + ch * sizeof(u32),
99 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_DMA_CH_RST_STS, val,
103 status = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_ERROR_STATUS);
104 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_DMA_ERR_STS_0 + ch * sizeof(u32));
106 dev_err(sdev->dev, "ACP_DMA_ERR_STS :0x%x ACP_ERROR_STATUS :0x%x\n", val, status);
110 snd_sof_dsp_write(sdev, ACP_DSP_BAR, (ACP_DMA_CNTL_0 + ch * sizeof(u32)), 0);
111 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_DSCR_CNT_0 + ch * sizeof(u32), dscr_count);
112 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_DSCR_STRT_IDX_0 + ch * sizeof(u32), idx);
113 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_PRIO_0 + ch * sizeof(u32), 0);
114 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_CNTL_0 + ch * sizeof(u32), ACP_DMA_CH_RUN);
122 struct snd_sof_dev *sdev = adata->dev;
134 dev_err(sdev->dev, "config dma ch failed:%d\n", ret);
142 struct snd_sof_dev *sdev = adata->dev;
157 dev_err(sdev->dev, "acpbus_dma_start failed\n");
174 struct snd_sof_dev *sdev = adata->dev;
183 dev_err(sdev->dev, "PSP error status %x\n", data & MBOX_STATUS_MASK);
199 struct snd_sof_dev *sdev = adata->dev;
211 dev_err(sdev->dev, "Failed to get Doorbell from MBOX %x\n", MP0_C2PMSG_73_REG);
235 struct snd_sof_dev *sdev = adata->dev;
236 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
241 dev_err(sdev->dev, "SHA DMA image address is NULL\n");
245 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD);
247 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD, ACP_SHA_RESET);
248 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD_STS,
253 dev_err(sdev->dev, "SHA DMA Failed to Reset\n");
259 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_INCLUDE_HDR, ACP_SHA_HEADER);
261 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_STRT_ADDR, start_addr);
262 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_DESTINATION_ADDR, dest_addr);
263 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_MSG_LENGTH, image_length);
264 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD, ACP_SHA_RUN);
266 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SHA_TRANSFER_BYTE_CNT,
270 dev_err(sdev->dev, "SHA DMA Failed to Transfer Length %x\n", tx_count);
281 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SHA_DSP_FW_QUALIFIER,
285 dev_err(sdev->dev, "PSP validation failed\n");
294 struct snd_sof_dev *sdev = adata->dev;
298 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_DMA_CNTL_0 + ch * sizeof(u32));
300 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_DMA_CH_STS, val, !val,
304 dev_err(sdev->dev, "DMA_CHANNEL %d status timeout\n", ch);
310 void memcpy_from_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *dst, size_t bytes)
316 dst[j] = snd_sof_dsp_read(sdev, ACP_DSP_BAR, reg_offset + i);
319 void memcpy_to_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *src, size_t bytes)
325 snd_sof_dsp_write(sdev, ACP_DSP_BAR, reg_offset + i, src[j]);
328 static int acp_memory_init(struct snd_sof_dev *sdev)
330 struct acp_dev_data *adata = sdev->pdata->hw_pdata;
331 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
333 snd_sof_dsp_update_bits(sdev, ACP_DSP_BAR, desc->dsp_intr_base + DSP_SW_INTR_CNTL_OFFSET,
342 struct snd_sof_dev *sdev = context;
343 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
346 while (snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->hw_semaphore_offset)) {
350 dev_err(sdev->dev, "%s: Failed to acquire HW lock\n", __func__);
355 sof_ops(sdev)->irq_thread(irq, sdev);
357 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->hw_semaphore_offset, 0x0);
364 struct snd_sof_dev *sdev = dev_id;
365 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
369 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, base + DSP_SW_INTR_STAT_OFFSET);
371 snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + DSP_SW_INTR_STAT_OFFSET,
379 static int acp_power_on(struct snd_sof_dev *sdev)
381 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
386 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, base + PGFSM_STATUS_OFFSET);
392 snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + PGFSM_CONTROL_OFFSET,
395 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, base + PGFSM_STATUS_OFFSET, val,
398 dev_err(sdev->dev, "timeout in ACP_PGFSM_STATUS read\n");
403 static int acp_reset(struct snd_sof_dev *sdev)
405 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
409 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, ACP_ASSERT_RESET);
411 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, val,
415 dev_err(sdev->dev, "timeout asserting reset\n");
419 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, ACP_RELEASE_RESET);
421 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, val, !val,
424 dev_err(sdev->dev, "timeout in releasing reset\n");
427 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->acp_clkmux_sel, ACP_CLOCK_ACLK);
430 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_enb, 0x01);
435 static int acp_init(struct snd_sof_dev *sdev)
440 ret = acp_power_on(sdev);
442 dev_err(sdev->dev, "ACP power on failed\n");
446 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_CONTROL, 0x01);
448 return acp_reset(sdev);
451 int amd_sof_acp_suspend(struct snd_sof_dev *sdev, u32 target_state)
455 ret = acp_reset(sdev);
457 dev_err(sdev->dev, "ACP Reset failed\n");
461 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_CONTROL, 0x00);
467 int amd_sof_acp_resume(struct snd_sof_dev *sdev)
471 ret = acp_init(sdev);
473 dev_err(sdev->dev, "ACP Init failed\n");
476 return acp_memory_init(sdev);
480 int amd_sof_acp_probe(struct snd_sof_dev *sdev)
482 struct pci_dev *pci = to_pci_dev(sdev->dev);
483 struct snd_sof_pdata *plat_data = sdev->pdata;
490 chip = get_chip_info(sdev->pdata);
492 dev_err(sdev->dev, "no such device supported, chip id:%x\n", pci->device);
495 adata = devm_kzalloc(sdev->dev, sizeof(struct acp_dev_data),
500 adata->dev = sdev;
501 adata->dmic_dev = platform_device_register_data(sdev->dev, "dmic-codec",
504 dev_err(sdev->dev, "failed to register platform for dmic codec\n");
508 sdev->bar[ACP_DSP_BAR] = devm_ioremap(sdev->dev, addr, pci_resource_len(pci, ACP_DSP_BAR));
509 if (!sdev->bar[ACP_DSP_BAR]) {
510 dev_err(sdev->dev, "ioremap error\n");
517 sdev->pdata->hw_pdata = adata;
520 dev_err(sdev->dev, "Failed to get host bridge device\n");
525 sdev->ipc_irq = pci->irq;
526 ret = request_threaded_irq(sdev->ipc_irq, acp_irq_handler, acp_irq_thread,
527 IRQF_SHARED, "AudioDSP", sdev);
529 dev_err(sdev->dev, "failed to register IRQ %d\n",
530 sdev->ipc_irq);
534 ret = acp_init(sdev);
538 sdev->dsp_box.offset = 0;
539 sdev->dsp_box.size = BOX_SIZE_512;
541 sdev->host_box.offset = sdev->dsp_box.offset + sdev->dsp_box.size;
542 sdev->host_box.size = BOX_SIZE_512;
544 sdev->debug_box.offset = sdev->host_box.offset + sdev->host_box.size;
545 sdev->debug_box.size = BOX_SIZE_1024;
550 adata->fw_code_bin = devm_kasprintf(sdev->dev, GFP_KERNEL,
559 adata->fw_data_bin = devm_kasprintf(sdev->dev, GFP_KERNEL,
572 acp_memory_init(sdev);
574 acp_dsp_stream_init(sdev);
579 free_irq(sdev->ipc_irq, sdev);
588 int amd_sof_acp_remove(struct snd_sof_dev *sdev)
590 struct acp_dev_data *adata = sdev->pdata->hw_pdata;
595 if (sdev->ipc_irq)
596 free_irq(sdev->ipc_irq, sdev);
601 return acp_reset(sdev);