Lines Matching refs:sdev
18 void acp_mailbox_write(struct snd_sof_dev *sdev, u32 offset, void *message, size_t bytes)
20 memcpy_to_scratch(sdev, offset, message, bytes);
24 void acp_mailbox_read(struct snd_sof_dev *sdev, u32 offset, void *message, size_t bytes)
26 memcpy_from_scratch(sdev, offset, message, bytes);
32 struct snd_sof_dev *sdev = adata->dev;
33 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
36 swintr_trigger = snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->dsp_intr_base +
39 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->dsp_intr_base + DSP_SW_INTR_TRIG_OFFSET,
43 static void acp_ipc_host_msg_set(struct snd_sof_dev *sdev)
45 unsigned int host_msg = sdev->debug_box.offset +
48 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SCRATCH_REG_0 + host_msg, 1);
51 static void acp_dsp_ipc_host_done(struct snd_sof_dev *sdev)
53 unsigned int dsp_msg = sdev->debug_box.offset +
56 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SCRATCH_REG_0 + dsp_msg, 0);
59 static void acp_dsp_ipc_dsp_done(struct snd_sof_dev *sdev)
61 unsigned int dsp_ack = sdev->debug_box.offset +
64 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SCRATCH_REG_0 + dsp_ack, 0);
67 int acp_sof_ipc_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
69 struct acp_dev_data *adata = sdev->pdata->hw_pdata;
70 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
71 unsigned int offset = sdev->host_box.offset;
74 while (snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->hw_semaphore_offset)) {
78 dev_err(sdev->dev, "%s: Failed to acquire HW lock\n", __func__);
83 acp_mailbox_write(sdev, offset, msg->msg_data, msg->msg_size);
84 acp_ipc_host_msg_set(sdev);
90 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->hw_semaphore_offset, 0x0);
96 static void acp_dsp_ipc_get_reply(struct snd_sof_dev *sdev)
98 struct snd_sof_ipc_msg *msg = sdev->msg;
101 unsigned int offset = sdev->host_box.offset;
110 dev_warn(sdev->dev, "unexpected ipc interrupt raised!\n");
128 acp_mailbox_read(sdev, offset, &reply, sizeof(reply));
143 dev_err(sdev->dev, "reply expected %zu got %u bytes\n",
149 acp_mailbox_read(sdev, offset, msg->reply_data, msg->reply_size);
157 struct snd_sof_dev *sdev = context;
158 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
159 struct acp_dev_data *adata = sdev->pdata->hw_pdata;
160 unsigned int dsp_msg_write = sdev->debug_box.offset +
162 unsigned int dsp_ack_write = sdev->debug_box.offset +
168 if (sdev->first_boot && sdev->fw_state != SOF_FW_BOOT_COMPLETE) {
169 acp_mailbox_read(sdev, sdev->dsp_box.offset, &status, sizeof(status));
171 snd_sof_dsp_panic(sdev, sdev->dsp_box.offset + sizeof(status),
174 acp_mailbox_write(sdev, sdev->dsp_box.offset, &status, sizeof(status));
177 snd_sof_ipc_msgs_rx(sdev);
178 acp_dsp_ipc_host_done(sdev);
182 dsp_msg = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SCRATCH_REG_0 + dsp_msg_write);
184 snd_sof_ipc_msgs_rx(sdev);
185 acp_dsp_ipc_host_done(sdev);
189 dsp_ack = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SCRATCH_REG_0 + dsp_ack_write);
191 spin_lock_irq(&sdev->ipc_lock);
193 acp_dsp_ipc_get_reply(sdev);
194 snd_sof_ipc_reply(sdev, 0);
196 acp_dsp_ipc_dsp_done(sdev);
197 spin_unlock_irq(&sdev->ipc_lock);
201 acp_mailbox_read(sdev, sdev->debug_box.offset, &status, sizeof(u32));
203 snd_sof_dsp_panic(sdev, sdev->dsp_oops_offset, true);
205 acp_mailbox_write(sdev, sdev->debug_box.offset, &status, sizeof(status));
218 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->probe_reg_offset);
227 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->probe_reg_offset, posn);
234 dev_dbg_ratelimited(sdev->dev, "nothing to do in IPC IRQ thread\n");
240 int acp_sof_ipc_msg_data(struct snd_sof_dev *sdev, struct snd_sof_pcm_stream *sps,
243 unsigned int offset = sdev->dsp_box.offset;
245 if (!sps || !sdev->stream_box.size) {
246 acp_mailbox_read(sdev, offset, p, sz);
259 acp_mailbox_read(sdev, stream->posn_offset, p, sz);
266 int acp_set_stream_data_offset(struct snd_sof_dev *sdev,
274 if (posn_offset > sdev->stream_box.size ||
278 stream->posn_offset = sdev->stream_box.offset + posn_offset;
280 dev_dbg(sdev->dev, "pcm: stream dir %d, posn mailbox offset is %zu",
287 int acp_sof_ipc_get_mailbox_offset(struct snd_sof_dev *sdev)
289 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
295 int acp_sof_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id)