Lines Matching refs:SSICR
25 * SSICR
241 * It will set SSIWSR.CONT here, but SSICR.CKDV = 000
243 * SSICR.CKDV = 000 is not allowed either).
244 * Skip it. See SSICR.CKDV
322 * SSICR : FORCE, SCKD, SWSD
420 * The SWL and DWL bits in SSICR should be fixed at 32-bit
461 rsnd_mod_write(mod, SSICR, ssi->cr_own |
574 rsnd_mod_write(mod, SSICR, ssi->cr_own |
604 rsnd_mod_write(mod, SSICR, cr | ssi->cr_en);
618 rsnd_mod_write(mod, SSICR, cr); /* disabled all */