Lines Matching refs:ret
65 int ret = 0;
68 ret = pinctrl_select_state(i2s->pinctrl, i2s->bclk_on);
70 if (ret)
71 dev_err(i2s->dev, "bclk enable failed %d\n", ret);
73 return ret;
79 int ret = 0;
82 ret = pinctrl_select_state(i2s->pinctrl, i2s->bclk_off);
84 if (ret)
85 dev_err(i2s->dev, "bclk disable failed %d\n", ret);
87 return ret;
103 int ret;
105 ret = clk_prepare_enable(i2s->mclk);
106 if (ret) {
107 dev_err(i2s->dev, "clock enable failed %d\n", ret);
108 return ret;
114 ret = regcache_sync(i2s->regmap);
115 if (ret)
118 return ret;
129 int ret = 0;
133 ret = regmap_update_bits(i2s->regmap, I2S_DMACR,
136 if (ret < 0)
138 ret = regmap_update_bits(i2s->regmap, I2S_XFER,
141 if (ret < 0)
147 ret = regmap_update_bits(i2s->regmap, I2S_DMACR,
150 if (ret < 0)
154 ret = regmap_update_bits(i2s->regmap, I2S_XFER,
157 if (ret < 0)
160 ret = regmap_update_bits(i2s->regmap, I2S_CLR,
163 if (ret < 0)
165 ret = regmap_read_poll_timeout_atomic(i2s->regmap,
171 if (ret < 0)
172 dev_warn(i2s->dev, "fail to clear: %d\n", ret);
177 if (ret < 0)
180 return ret;
186 int ret = 0;
190 ret = regmap_update_bits(i2s->regmap, I2S_DMACR,
193 if (ret < 0)
196 ret = regmap_update_bits(i2s->regmap, I2S_XFER,
199 if (ret < 0)
205 ret = regmap_update_bits(i2s->regmap, I2S_DMACR,
208 if (ret < 0)
212 ret = regmap_update_bits(i2s->regmap, I2S_XFER,
215 if (ret < 0)
218 ret = regmap_update_bits(i2s->regmap, I2S_CLR,
221 if (ret < 0)
223 ret = regmap_read_poll_timeout_atomic(i2s->regmap,
229 if (ret < 0)
230 dev_warn(i2s->dev, "fail to clear: %d\n", ret);
235 if (ret < 0)
238 return ret;
246 int ret = 0;
261 ret = -EINVAL;
290 ret = -EINVAL;
314 ret = -EINVAL;
338 ret = -EINVAL;
347 return ret;
469 int ret = 0;
476 ret = rockchip_snd_rxctrl(i2s, 1);
478 ret = rockchip_snd_txctrl(i2s, 1);
479 if (ret < 0)
480 return ret;
489 ret = rockchip_snd_rxctrl(i2s, 0);
493 ret = rockchip_snd_txctrl(i2s, 0);
497 ret = -EINVAL;
501 return ret;
518 int ret;
523 ret = clk_set_rate(i2s->mclk, freq);
524 if (ret)
525 dev_err(i2s->dev, "Fail to set mclk %d\n", ret);
527 return ret;
744 int ret;
768 ret = clk_prepare_enable(i2s->hclk);
769 if (ret) {
770 dev_err(i2s->dev, "hclock enable failed %d\n", ret);
771 return ret;
777 ret = PTR_ERR(i2s->mclk);
783 ret = PTR_ERR(regs);
792 ret = PTR_ERR(i2s->regmap);
804 ret = -EINVAL;
818 ret = i2s_runtime_resume(&pdev->dev);
819 if (ret)
823 ret = rockchip_i2s_init_dai(i2s, res, &dai);
824 if (ret)
827 ret = devm_snd_soc_register_component(&pdev->dev,
831 if (ret) {
836 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
837 if (ret) {
851 return ret;