Lines Matching defs:SACR0
31 #define SACR0 (0x0000) /* Global Control Register */
103 writel(0, i2s_reg_base + SACR0);
174 if (!(SACR0 & SACR0_ENB)) {
175 writel(0, i2s_reg_base + SACR0);
177 writel(readl(i2s_reg_base + SACR0) | (SACR0_BCKD), i2s_reg_base + SACR0);
179 writel(readl(i2s_reg_base + SACR0) | (SACR0_RFTH(14) | SACR0_TFTH(1)), i2s_reg_base + SACR0);
225 writel(readl(i2s_reg_base + SACR0) | (SACR0_ENB), i2s_reg_base + SACR0);
252 writel(readl(i2s_reg_base + SACR0) & (~SACR0_ENB), i2s_reg_base + SACR0);
265 pxa_i2s.sacr0 = readl(i2s_reg_base + SACR0);
271 writel(readl(i2s_reg_base + SACR0) & (~SACR0_ENB), i2s_reg_base + SACR0);
280 writel(pxa_i2s.sacr0 & ~SACR0_ENB, i2s_reg_base + SACR0);
285 writel(pxa_i2s.sacr0, i2s_reg_base + SACR0);
303 * If SACR0[ENB] is toggled in the middle of a normal operation,
304 * the SACR0[RST] bit must also be set and cleared to reset all
307 writel(SACR0_RST, i2s_reg_base + SACR0);
308 writel(0, i2s_reg_base + SACR0);