Lines Matching defs:saif
23 #include "mxs-saif.h"
40 * We abstract this as each saif has a master, the master could be
41 * itself or other saifs. In the generic saif driver, saif does not need
51 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
55 saif->mclk = freq;
69 static inline struct mxs_saif *mxs_saif_get_master(struct mxs_saif * saif)
71 return mxs_saif[saif->master_id];
77 static int mxs_saif_set_clk(struct mxs_saif *saif,
85 dev_dbg(saif->dev, "mclk %d rate %d\n", mclk, rate);
87 /* Set master saif to generate proper clock */
88 master_saif = mxs_saif_get_master(saif);
92 dev_dbg(saif->dev, "master saif%d\n", master_saif->id);
96 dev_err(saif->dev,
97 "can not change clock, master saif%d(rate %d) is ongoing\n",
111 * For 256x, 128x, 64x, and 32x sub-rates, set saif clk as 512*fs.
112 * For 192x, 96x, and 48x sub-rates, set saif clk as 384*fs.
114 * If MCLK is not used, we just set saif clk to 512*fs.
207 struct mxs_saif *saif = mxs_saif[saif_id];
210 if (!saif)
213 stat = __raw_readl(saif->base + SAIF_STAT);
215 dev_err(saif->dev, "error: busy\n");
219 clk_disable_unprepare(saif->clk);
223 saif->base + SAIF_CTRL + MXS_SET_ADDR);
225 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
227 saif->mclk_in_use = 0;
236 * by saif.
241 struct mxs_saif *saif = mxs_saif[saif_id];
246 if (!saif)
251 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
255 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
257 master_saif = mxs_saif_get_master(saif);
258 if (saif != master_saif) {
259 dev_err(saif->dev, "can not get mclk from a non-master saif\n");
263 stat = __raw_readl(saif->base + SAIF_STAT);
265 dev_err(saif->dev, "error: busy\n");
269 saif->mclk_in_use = 1;
270 ret = mxs_saif_set_clk(saif, mclk, rate);
274 ret = clk_prepare_enable(saif->clk);
280 saif->base + SAIF_CTRL + MXS_SET_ADDR);
294 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
296 stat = __raw_readl(saif->base + SAIF_STAT);
305 if (saif->id != saif->master_id) {
307 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
309 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
312 scr0 = __raw_readl(saif->base + SAIF_CTRL);
363 if (saif->id == saif->master_id)
368 __raw_writel(scr | scr0, saif->base + SAIF_CTRL);
380 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
384 saif->fifo_underrun = 0;
385 saif->fifo_overrun = 0;
389 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
393 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
395 ret = clk_prepare(saif->clk);
405 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
407 clk_unprepare(saif->clk);
418 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
423 master_saif = mxs_saif_get_master(saif);
428 if (!saif->mclk && saif->mclk_in_use) {
433 stat = __raw_readl(saif->base + SAIF_STAT);
434 if (!saif->mclk_in_use && (stat & BM_SAIF_STAT_BUSY)) {
440 * Set saif clk based on sample rate.
441 * If mclk is used, we also set mclk, if not, saif->mclk is
444 ret = mxs_saif_set_clk(saif, saif->mclk, params_rate(params));
450 if (saif != master_saif) {
452 * Set an initial clock rate for the saif internal logic to work
454 * that uses the other saif's BITCLK&LRCLK but it still needs a
458 ret = clk_enable(saif->clk);
462 ret = clk_set_rate(saif->clk, 24000000);
463 clk_disable(saif->clk);
472 scr = __raw_readl(saif->base + SAIF_CTRL);
501 __raw_writel(scr, saif->base + SAIF_CTRL);
508 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
512 saif->base + SAIF_CTRL + MXS_SET_ADDR);
520 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
525 master_saif = mxs_saif_get_master(saif);
533 if (saif->state == MXS_SAIF_STATE_RUNNING)
540 dev_err(saif->dev, "Failed to enable master clock\n");
545 * If the saif's master is not itself, we also need to enable
548 if (saif != master_saif) {
549 ret = clk_enable(saif->clk);
551 dev_err(saif->dev, "Failed to enable master clock\n");
557 saif->base + SAIF_CTRL + MXS_SET_ADDR);
566 * write data to saif data register to trigger
572 __raw_writel(0, saif->base + SAIF_DATA);
573 __raw_writel(0, saif->base + SAIF_DATA);
576 * read data from saif data register to trigger
582 __raw_readl(saif->base + SAIF_DATA);
583 __raw_readl(saif->base + SAIF_DATA);
587 saif->state = MXS_SAIF_STATE_RUNNING;
589 dev_dbg(saif->dev, "CTRL 0x%x STAT 0x%x\n",
590 __raw_readl(saif->base + SAIF_CTRL),
591 __raw_readl(saif->base + SAIF_STAT));
600 if (saif->state == MXS_SAIF_STATE_STOPPED)
615 if (saif != master_saif) {
617 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
619 clk_disable(saif->clk);
623 saif->state = MXS_SAIF_STATE_STOPPED;
649 .name = "mxs-saif",
666 .name = "mxs-saif",
672 struct mxs_saif *saif = dev_id;
675 stat = __raw_readl(saif->base + SAIF_STAT);
681 dev_dbg(saif->dev, "underrun!!! %d\n", ++saif->fifo_underrun);
683 saif->base + SAIF_STAT + MXS_CLR_ADDR);
687 dev_dbg(saif->dev, "overrun!!! %d\n", ++saif->fifo_overrun);
689 saif->base + SAIF_STAT + MXS_CLR_ADDR);
692 dev_dbg(saif->dev, "SAIF_CTRL %x SAIF_STAT %x\n",
693 __raw_readl(saif->base + SAIF_CTRL),
694 __raw_readl(saif->base + SAIF_STAT));
701 struct mxs_saif *saif = platform_get_drvdata(pdev);
707 __clk_get_name(saif->clk), 0,
708 saif->base + SAIF_CTRL,
729 struct mxs_saif *saif;
733 saif = devm_kzalloc(&pdev->dev, sizeof(*saif), GFP_KERNEL);
734 if (!saif)
737 ret = of_alias_get_id(np, "saif");
741 saif->id = ret;
743 if (saif->id >= ARRAY_SIZE(mxs_saif)) {
744 dev_err(&pdev->dev, "get wrong saif id\n");
749 * If there is no "fsl,saif-master" phandle, it's a saif
753 master = of_parse_phandle(np, "fsl,saif-master", 0);
755 saif->master_id = saif->id;
757 ret = of_alias_get_id(master, "saif");
762 saif->master_id = ret;
764 if (saif->master_id >= ARRAY_SIZE(mxs_saif)) {
770 mxs_saif[saif->id] = saif;
772 saif->clk = devm_clk_get(&pdev->dev, NULL);
773 if (IS_ERR(saif->clk)) {
774 ret = PTR_ERR(saif->clk);
780 saif->base = devm_platform_ioremap_resource(pdev, 0);
781 if (IS_ERR(saif->base))
782 return PTR_ERR(saif->base);
788 saif->dev = &pdev->dev;
790 dev_name(&pdev->dev), saif);
796 platform_set_drvdata(pdev, saif);
799 if (saif->id == 0) {
822 { .compatible = "fsl,imx28-saif", },
831 .name = "mxs-saif",
841 MODULE_ALIAS("platform:mxs-saif");