Lines Matching refs:fifo
16 #include "axg-fifo.h"
20 * capture frontend DAI. The logic behind this two types of fifo is very
67 static void __dma_enable(struct axg_fifo *fifo, bool enable)
69 regmap_update_bits(fifo->map, FIFO_CTRL0, CTRL0_DMA_EN,
76 struct axg_fifo *fifo = axg_fifo_data(ss);
82 __dma_enable(fifo, true);
87 __dma_enable(fifo, false);
100 struct axg_fifo *fifo = axg_fifo_data(ss);
104 regmap_read(fifo->map, FIFO_STATUS2, &addr);
115 struct axg_fifo *fifo = axg_fifo_data(ss);
123 regmap_write(fifo->map, FIFO_START_ADDR, runtime->dma_addr);
124 regmap_write(fifo->map, FIFO_FINISH_ADDR, end_ptr);
128 regmap_write(fifo->map, FIFO_INT_ADDR, burst_num);
131 * Start the fifo request on the smallest of the following:
132 * - Half the fifo size
135 threshold = min(period / 2, fifo->depth / 2);
142 regmap_field_write(fifo->field_threshold,
147 regmap_update_bits(fifo->map, FIFO_CTRL0,
159 struct axg_fifo *fifo = axg_fifo_data(ss);
168 regmap_write(fifo->map, FIFO_INIT_ADDR, runtime->dma_addr);
177 struct axg_fifo *fifo = axg_fifo_data(ss);
180 regmap_update_bits(fifo->map, FIFO_CTRL0,
187 static void axg_fifo_ack_irq(struct axg_fifo *fifo, u8 mask)
189 regmap_update_bits(fifo->map, FIFO_CTRL1,
194 regmap_update_bits(fifo->map, FIFO_CTRL1,
202 struct axg_fifo *fifo = axg_fifo_data(ss);
205 regmap_read(fifo->map, FIFO_STATUS1, &status);
215 axg_fifo_ack_irq(fifo, status);
223 struct axg_fifo *fifo = axg_fifo_data(ss);
245 ret = request_irq(fifo->irq, axg_fifo_pcm_irq_block, 0,
250 /* Enable pclk to access registers and clock the fifo ip */
251 ret = clk_prepare_enable(fifo->pclk);
256 regmap_update_bits(fifo->map, FIFO_CTRL1,
261 __dma_enable(fifo, false);
264 regmap_update_bits(fifo->map, FIFO_CTRL0,
268 axg_fifo_ack_irq(fifo, FIFO_INT_MASK);
271 ret = reset_control_deassert(fifo->arb);
278 clk_disable_unprepare(fifo->pclk);
280 free_irq(fifo->irq, ss);
288 struct axg_fifo *fifo = axg_fifo_data(ss);
292 ret = reset_control_assert(fifo->arb);
294 /* Disable fifo ip and register access */
295 clk_disable_unprepare(fifo->pclk);
298 free_irq(fifo->irq, ss);
327 struct axg_fifo *fifo;
337 fifo = devm_kzalloc(dev, sizeof(*fifo), GFP_KERNEL);
338 if (!fifo)
340 platform_set_drvdata(pdev, fifo);
346 fifo->map = devm_regmap_init_mmio(dev, regs, &axg_fifo_regmap_cfg);
347 if (IS_ERR(fifo->map)) {
349 PTR_ERR(fifo->map));
350 return PTR_ERR(fifo->map);
353 fifo->pclk = devm_clk_get(dev, NULL);
354 if (IS_ERR(fifo->pclk))
355 return dev_err_probe(dev, PTR_ERR(fifo->pclk), "failed to get pclk\n");
357 fifo->arb = devm_reset_control_get_exclusive(dev, NULL);
358 if (IS_ERR(fifo->arb))
359 return dev_err_probe(dev, PTR_ERR(fifo->arb), "failed to get arb reset\n");
361 fifo->irq = of_irq_get(dev->of_node, 0);
362 if (fifo->irq <= 0) {
363 dev_err(dev, "failed to get irq: %d\n", fifo->irq);
364 return fifo->irq;
367 fifo->field_threshold =
368 devm_regmap_field_alloc(dev, fifo->map, data->field_threshold);
369 if (IS_ERR(fifo->field_threshold))
370 return PTR_ERR(fifo->field_threshold);
372 ret = of_property_read_u32(dev->of_node, "amlogic,fifo-depth",
373 &fifo->depth);
380 * DT. In such case, assume the smallest known fifo depth
382 fifo->depth = 256;
383 dev_warn(dev, "fifo depth not found, assume %u bytes\n",
384 fifo->depth);
392 MODULE_DESCRIPTION("Amlogic AXG/G12A fifo driver");