Lines Matching refs:afe
3 * mt8195-afe-clk.c -- Mediatek 8195 afe clock ctrl
12 #include "mt8195-afe-common.h"
13 #include "mt8195-afe-clk.h"
41 /* afe clock gate */
217 static int mt8195_afe_setup_apll_tuner(struct mtk_base_afe *afe,
225 regmap_update_bits(afe->regmap, cfg->apll_div_reg,
229 regmap_update_bits(afe->regmap, cfg->ref_ck_sel_reg,
233 regmap_update_bits(afe->regmap, cfg->upper_bound_reg,
240 static int mt8195_afe_enable_tuner_clk(struct mtk_base_afe *afe,
243 struct mt8195_afe_private *afe_priv = afe->platform_priv;
247 mt8195_afe_enable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL]);
248 mt8195_afe_enable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL1_TUNER]);
251 mt8195_afe_enable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL2]);
252 mt8195_afe_enable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL2_TUNER]);
261 static int mt8195_afe_disable_tuner_clk(struct mtk_base_afe *afe,
264 struct mt8195_afe_private *afe_priv = afe->platform_priv;
268 mt8195_afe_disable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL1_TUNER]);
269 mt8195_afe_disable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL]);
272 mt8195_afe_disable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL2_TUNER]);
273 mt8195_afe_disable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL2]);
282 static int mt8195_afe_enable_apll_tuner(struct mtk_base_afe *afe,
292 ret = mt8195_afe_setup_apll_tuner(afe, id);
296 ret = mt8195_afe_enable_tuner_clk(afe, id);
304 regmap_update_bits(afe->regmap,
314 static int mt8195_afe_disable_apll_tuner(struct mtk_base_afe *afe,
328 regmap_update_bits(afe->regmap,
337 ret = mt8195_afe_disable_tuner_clk(afe, id);
358 int mt8195_afe_get_mclk_source_rate(struct mtk_base_afe *afe, int apll)
360 struct mt8195_afe_private *afe_priv = afe->platform_priv;
364 dev_dbg(afe->dev, "invalid clk id\n");
377 int mt8195_afe_init_clock(struct mtk_base_afe *afe)
379 struct mt8195_afe_private *afe_priv = afe->platform_priv;
382 mt8195_audsys_clk_register(afe);
385 devm_kcalloc(afe->dev, MT8195_CLK_NUM, sizeof(*afe_priv->clk),
391 afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]);
393 dev_dbg(afe->dev, "%s(), devm_clk_get %s fail, ret %ld\n",
404 dev_dbg(afe->dev, "%s(), init apll_tuner%d failed",
413 int mt8195_afe_enable_clk(struct mtk_base_afe *afe, struct clk *clk)
420 dev_dbg(afe->dev, "%s(), failed to enable clk\n",
425 dev_dbg(afe->dev, "NULL clk\n");
431 void mt8195_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk)
436 dev_dbg(afe->dev, "NULL clk\n");
440 int mt8195_afe_prepare_clk(struct mtk_base_afe *afe, struct clk *clk)
447 dev_dbg(afe->dev, "%s(), failed to prepare clk\n",
452 dev_dbg(afe->dev, "NULL clk\n");
457 void mt8195_afe_unprepare_clk(struct mtk_base_afe *afe, struct clk *clk)
462 dev_dbg(afe->dev, "NULL clk\n");
465 int mt8195_afe_enable_clk_atomic(struct mtk_base_afe *afe, struct clk *clk)
472 dev_dbg(afe->dev, "%s(), failed to clk enable\n",
477 dev_dbg(afe->dev, "NULL clk\n");
482 void mt8195_afe_disable_clk_atomic(struct mtk_base_afe *afe, struct clk *clk)
487 dev_dbg(afe->dev, "NULL clk\n");
490 int mt8195_afe_set_clk_rate(struct mtk_base_afe *afe, struct clk *clk,
498 dev_dbg(afe->dev, "%s(), failed to set clk rate\n",
507 int mt8195_afe_set_clk_parent(struct mtk_base_afe *afe, struct clk *clk,
515 dev_dbg(afe->dev, "%s(), failed to set clk parent\n",
574 static int mt8195_afe_enable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type)
580 regmap_update_bits(afe->regmap, reg, mask, val);
584 static int mt8195_afe_disable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type)
590 regmap_update_bits(afe->regmap, reg, mask, val);
594 int mt8195_afe_enable_reg_rw_clk(struct mtk_base_afe *afe)
596 struct mt8195_afe_private *afe_priv = afe->platform_priv;
610 mt8195_afe_enable_clk(afe, afe_priv->clk[clk_array[i]]);
615 int mt8195_afe_disable_reg_rw_clk(struct mtk_base_afe *afe)
617 struct mt8195_afe_private *afe_priv = afe->platform_priv;
631 mt8195_afe_disable_clk(afe, afe_priv->clk[clk_array[i]]);
636 static int mt8195_afe_enable_afe_on(struct mtk_base_afe *afe)
638 regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x1);
642 static int mt8195_afe_disable_afe_on(struct mtk_base_afe *afe)
644 regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x0);
648 static int mt8195_afe_enable_timing_sys(struct mtk_base_afe *afe)
650 struct mt8195_afe_private *afe_priv = afe->platform_priv;
663 mt8195_afe_enable_clk(afe, afe_priv->clk[clk_array[i]]);
666 mt8195_afe_enable_top_cg(afe, cg_array[i]);
671 static int mt8195_afe_disable_timing_sys(struct mtk_base_afe *afe)
673 struct mt8195_afe_private *afe_priv = afe->platform_priv;
686 mt8195_afe_disable_top_cg(afe, cg_array[i]);
689 mt8195_afe_disable_clk(afe, afe_priv->clk[clk_array[i]]);
694 int mt8195_afe_enable_main_clock(struct mtk_base_afe *afe)
696 mt8195_afe_enable_timing_sys(afe);
698 mt8195_afe_enable_afe_on(afe);
700 mt8195_afe_enable_apll_tuner(afe, MT8195_AUD_PLL1);
701 mt8195_afe_enable_apll_tuner(afe, MT8195_AUD_PLL2);
706 int mt8195_afe_disable_main_clock(struct mtk_base_afe *afe)
708 mt8195_afe_disable_apll_tuner(afe, MT8195_AUD_PLL2);
709 mt8195_afe_disable_apll_tuner(afe, MT8195_AUD_PLL1);
711 mt8195_afe_disable_afe_on(afe);
713 mt8195_afe_disable_timing_sys(afe);