Lines Matching refs:afe
3 // mt8192-afe-clk.c -- Mediatek 8192 afe clock ctrl
14 #include "mt8192-afe-clk.h"
15 #include "mt8192-afe-common.h"
63 int mt8192_set_audio_int_bus_parent(struct mtk_base_afe *afe,
66 struct mt8192_afe_private *afe_priv = afe->platform_priv;
72 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
80 static int apll1_mux_setting(struct mtk_base_afe *afe, bool enable)
82 struct mt8192_afe_private *afe_priv = afe->platform_priv;
88 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
95 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
104 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
111 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
120 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
130 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
142 static int apll2_mux_setting(struct mtk_base_afe *afe, bool enable)
144 struct mt8192_afe_private *afe_priv = afe->platform_priv;
150 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
157 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
166 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
173 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
182 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
192 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
204 int mt8192_afe_enable_clock(struct mtk_base_afe *afe)
206 struct mt8192_afe_private *afe_priv = afe->platform_priv;
211 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
218 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
225 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
232 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
240 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
245 ret = mt8192_set_audio_int_bus_parent(afe, CLK_CLK26M);
247 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
256 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
264 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
273 void mt8192_afe_disable_clock(struct mtk_base_afe *afe)
275 struct mt8192_afe_private *afe_priv = afe->platform_priv;
278 mt8192_set_audio_int_bus_parent(afe, CLK_CLK26M);
285 int mt8192_apll1_enable(struct mtk_base_afe *afe)
287 struct mt8192_afe_private *afe_priv = afe->platform_priv;
291 apll1_mux_setting(afe, true);
295 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
302 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
307 regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG,
309 regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG, 0x1, 0x1);
311 regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
319 void mt8192_apll1_disable(struct mtk_base_afe *afe)
321 struct mt8192_afe_private *afe_priv = afe->platform_priv;
323 regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
327 regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG, 0x1, 0x0);
332 apll1_mux_setting(afe, false);
335 int mt8192_apll2_enable(struct mtk_base_afe *afe)
337 struct mt8192_afe_private *afe_priv = afe->platform_priv;
341 apll2_mux_setting(afe, true);
345 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
352 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
357 regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG,
359 regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG, 0x1, 0x1);
361 regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
369 void mt8192_apll2_disable(struct mtk_base_afe *afe)
371 struct mt8192_afe_private *afe_priv = afe->platform_priv;
373 regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
377 regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG, 0x1, 0x0);
382 apll2_mux_setting(afe, false);
385 int mt8192_get_apll_rate(struct mtk_base_afe *afe, int apll)
390 int mt8192_get_apll_by_rate(struct mtk_base_afe *afe, int rate)
395 int mt8192_get_apll_by_name(struct mtk_base_afe *afe, const char *name)
562 int mt8192_mck_enable(struct mtk_base_afe *afe, int mck_id, int rate)
564 struct mt8192_afe_private *afe_priv = afe->platform_priv;
565 int apll = mt8192_get_apll_by_rate(afe, rate);
576 dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",
583 dev_err(afe->dev, "%s(), clk_set_parent %s-%s fail %d\n",
593 dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",
599 dev_err(afe->dev, "%s(), clk_set_rate %s, rate %d, fail %d\n",
608 void mt8192_mck_disable(struct mtk_base_afe *afe, int mck_id)
610 struct mt8192_afe_private *afe_priv = afe->platform_priv;
619 int mt8192_init_clock(struct mtk_base_afe *afe)
621 struct mt8192_afe_private *afe_priv = afe->platform_priv;
622 struct device_node *of_node = afe->dev->of_node;
625 afe_priv->clk = devm_kcalloc(afe->dev, CLK_NUM, sizeof(*afe_priv->clk),
631 afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]);
633 dev_warn(afe->dev, "%s devm_clk_get %s fail, ret %ld\n",
643 dev_err(afe->dev, "%s() Cannot find apmixedsys controller: %ld\n",
651 dev_err(afe->dev, "%s() Cannot find topckgen controller: %ld\n",
659 dev_err(afe->dev, "%s() Cannot find infracfg: %ld\n",