Lines Matching defs:ret
67 int ret;
69 ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIOINTBUS],
71 if (ret) {
74 aud_clks[clk_id], ret);
77 return ret;
83 int ret;
86 ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_1]);
87 if (ret) {
89 __func__, aud_clks[CLK_TOP_MUX_AUD_1], ret);
92 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1],
94 if (ret) {
97 aud_clks[CLK_TOP_APLL1_CK], ret);
102 ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1]);
103 if (ret) {
105 __func__, aud_clks[CLK_TOP_MUX_AUD_ENG1], ret);
108 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1],
110 if (ret) {
113 aud_clks[CLK_TOP_APLL1_D4], ret);
117 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1],
119 if (ret) {
122 aud_clks[CLK_CLK26M], ret);
127 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1],
129 if (ret) {
132 aud_clks[CLK_CLK26M], ret);
139 return ret;
145 int ret;
148 ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_2]);
149 if (ret) {
151 __func__, aud_clks[CLK_TOP_MUX_AUD_2], ret);
154 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2],
156 if (ret) {
159 aud_clks[CLK_TOP_APLL2_CK], ret);
164 ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2]);
165 if (ret) {
167 __func__, aud_clks[CLK_TOP_MUX_AUD_ENG2], ret);
170 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2],
172 if (ret) {
175 aud_clks[CLK_TOP_APLL2_D4], ret);
179 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2],
181 if (ret) {
184 aud_clks[CLK_CLK26M], ret);
189 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2],
191 if (ret) {
194 aud_clks[CLK_CLK26M], ret);
201 return ret;
207 int ret;
209 ret = clk_prepare_enable(afe_priv->clk[CLK_INFRA_SYS_AUDIO]);
210 if (ret) {
212 __func__, aud_clks[CLK_INFRA_SYS_AUDIO], ret);
216 ret = clk_prepare_enable(afe_priv->clk[CLK_INFRA_AUDIO_26M]);
217 if (ret) {
219 __func__, aud_clks[CLK_INFRA_AUDIO_26M], ret);
223 ret = clk_prepare_enable(afe_priv->clk[CLK_MUX_AUDIO]);
224 if (ret) {
226 __func__, aud_clks[CLK_MUX_AUDIO], ret);
229 ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIO],
231 if (ret) {
234 aud_clks[CLK_CLK26M], ret);
238 ret = clk_prepare_enable(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
239 if (ret) {
241 __func__, aud_clks[CLK_MUX_AUDIOINTBUS], ret);
245 ret = mt8192_set_audio_int_bus_parent(afe, CLK_CLK26M);
246 if (ret) {
249 aud_clks[CLK_CLK26M], ret);
253 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUDIO_H],
255 if (ret) {
258 aud_clks[CLK_TOP_APLL2_CK], ret);
262 ret = clk_prepare_enable(afe_priv->clk[CLK_AFE]);
263 if (ret) {
265 __func__, aud_clks[CLK_AFE], ret);
270 return ret;
288 int ret;
293 ret = clk_prepare_enable(afe_priv->clk[CLK_APLL22M]);
294 if (ret) {
296 __func__, aud_clks[CLK_APLL22M], ret);
300 ret = clk_prepare_enable(afe_priv->clk[CLK_APLL1_TUNER]);
301 if (ret) {
303 __func__, aud_clks[CLK_APLL1_TUNER], ret);
316 return ret;
338 int ret;
343 ret = clk_prepare_enable(afe_priv->clk[CLK_APLL24M]);
344 if (ret) {
346 __func__, aud_clks[CLK_APLL24M], ret);
350 ret = clk_prepare_enable(afe_priv->clk[CLK_APLL2_TUNER]);
351 if (ret) {
353 __func__, aud_clks[CLK_APLL2_TUNER], ret);
366 return ret;
570 int ret;
574 ret = clk_prepare_enable(afe_priv->clk[m_sel_id]);
575 if (ret) {
577 __func__, aud_clks[m_sel_id], ret);
578 return ret;
580 ret = clk_set_parent(afe_priv->clk[m_sel_id],
582 if (ret) {
585 aud_clks[apll_clk_id], ret);
586 return ret;
591 ret = clk_prepare_enable(afe_priv->clk[div_clk_id]);
592 if (ret) {
594 __func__, aud_clks[div_clk_id], ret);
595 return ret;
597 ret = clk_set_rate(afe_priv->clk[div_clk_id], rate);
598 if (ret) {
601 rate, ret);
602 return ret;
633 dev_warn(afe->dev, "%s devm_clk_get %s fail, ret %ld\n",