Lines Matching refs:afe_priv
254 struct mt8188_afe_private *afe_priv = afe->platform_priv;
258 mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL]);
259 mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL1_TUNER]);
262 mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL2]);
263 mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL2_TUNER]);
275 struct mt8188_afe_private *afe_priv = afe->platform_priv;
279 mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL1_TUNER]);
280 mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL]);
283 mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL2_TUNER]);
284 mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL2]);
369 struct mt8188_afe_private *afe_priv = afe->platform_priv;
377 return clk_get_rate(afe_priv->clk[clk_id]);
401 struct mt8188_afe_private *afe_priv = afe->platform_priv;
410 afe_priv->clk =
411 devm_kcalloc(afe->dev, MT8188_CLK_NUM, sizeof(*afe_priv->clk),
413 if (!afe_priv->clk)
417 afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]);
418 if (IS_ERR(afe_priv->clk[i])) {
421 PTR_ERR(afe_priv->clk[i]));
422 return PTR_ERR(afe_priv->clk[i]);
574 struct mt8188_afe_private *afe_priv = afe->platform_priv;
577 mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_AUDIO_LOCAL_BUS_SEL]);
580 mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_AUD_INTBUS_SEL]);
583 mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_ADSP_AUDIO_26M]);
586 mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_AFE]);
587 mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS_HP]);
588 mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS]);
595 struct mt8188_afe_private *afe_priv = afe->platform_priv;
597 mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS]);
598 mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS_HP]);
599 mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_AFE]);
600 mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_ADSP_AUDIO_26M]);
601 mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_AUD_INTBUS_SEL]);
602 mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_AUDIO_LOCAL_BUS_SEL]);
621 struct mt8188_afe_private *afe_priv = afe->platform_priv;
624 ret = mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS]);
633 struct mt8188_afe_private *afe_priv = afe->platform_priv;
636 mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS]);
642 struct mt8188_afe_private *afe_priv = afe->platform_priv;
645 ret = mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A2SYS]);
654 struct mt8188_afe_private *afe_priv = afe->platform_priv;
657 mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A2SYS]);
663 struct mt8188_afe_private *afe_priv = afe->platform_priv;
666 ret = mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_APLL1_D4]);
670 ret = mt8188_afe_set_clk_parent(afe, afe_priv->clk[MT8188_CLK_TOP_A1SYS_HP_SEL],
671 afe_priv->clk[MT8188_CLK_TOP_APLL1_D4]);
688 mt8188_afe_set_clk_parent(afe, afe_priv->clk[MT8188_CLK_TOP_A1SYS_HP_SEL],
689 afe_priv->clk[MT8188_CLK_XTAL_26M]);
691 mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_APLL1_D4]);
698 struct mt8188_afe_private *afe_priv = afe->platform_priv;
702 mt8188_afe_set_clk_parent(afe, afe_priv->clk[MT8188_CLK_TOP_A1SYS_HP_SEL],
703 afe_priv->clk[MT8188_CLK_XTAL_26M]);
704 mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_APLL1_D4]);