Lines Matching refs:afe
3 * mt8188-afe-clk.c -- MediaTek 8188 afe clock ctrl
13 #include "mt8188-afe-common.h"
14 #include "mt8188-afe-clk.h"
51 /* afe clock gate */
226 static int mt8188_afe_setup_apll_tuner(struct mtk_base_afe *afe, unsigned int id)
233 regmap_update_bits(afe->regmap,
238 regmap_update_bits(afe->regmap,
243 regmap_update_bits(afe->regmap,
251 static int mt8188_afe_enable_tuner_clk(struct mtk_base_afe *afe,
254 struct mt8188_afe_private *afe_priv = afe->platform_priv;
258 mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL]);
259 mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL1_TUNER]);
262 mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL2]);
263 mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL2_TUNER]);
272 static int mt8188_afe_disable_tuner_clk(struct mtk_base_afe *afe,
275 struct mt8188_afe_private *afe_priv = afe->platform_priv;
279 mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL1_TUNER]);
280 mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL]);
283 mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL2_TUNER]);
284 mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL2]);
293 static int mt8188_afe_enable_apll_tuner(struct mtk_base_afe *afe, unsigned int id)
302 ret = mt8188_afe_setup_apll_tuner(afe, id);
306 ret = mt8188_afe_enable_tuner_clk(afe, id);
314 regmap_update_bits(afe->regmap,
324 static int mt8188_afe_disable_apll_tuner(struct mtk_base_afe *afe, unsigned int id)
337 regmap_update_bits(afe->regmap,
346 ret = mt8188_afe_disable_tuner_clk(afe, id);
367 int mt8188_afe_get_mclk_source_rate(struct mtk_base_afe *afe, int apll)
369 struct mt8188_afe_private *afe_priv = afe->platform_priv;
373 dev_dbg(afe->dev, "invalid clk id\n");
386 int mt8188_get_apll_by_rate(struct mtk_base_afe *afe, int rate)
391 int mt8188_get_apll_by_name(struct mtk_base_afe *afe, const char *name)
399 int mt8188_afe_init_clock(struct mtk_base_afe *afe)
401 struct mt8188_afe_private *afe_priv = afe->platform_priv;
404 ret = mt8188_audsys_clk_register(afe);
406 dev_err(afe->dev, "register audsys clk fail %d\n", ret);
411 devm_kcalloc(afe->dev, MT8188_CLK_NUM, sizeof(*afe_priv->clk),
417 afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]);
419 dev_err(afe->dev, "%s(), devm_clk_get %s fail, ret %ld\n",
430 dev_info(afe->dev, "%s(), init apll_tuner%d failed",
439 int mt8188_afe_enable_clk(struct mtk_base_afe *afe, struct clk *clk)
446 dev_dbg(afe->dev, "%s(), failed to enable clk\n",
451 dev_dbg(afe->dev, "NULL clk\n");
457 void mt8188_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk)
462 dev_dbg(afe->dev, "NULL clk\n");
466 int mt8188_afe_set_clk_rate(struct mtk_base_afe *afe, struct clk *clk,
474 dev_dbg(afe->dev, "%s(), failed to set clk rate\n",
483 int mt8188_afe_set_clk_parent(struct mtk_base_afe *afe, struct clk *clk,
491 dev_dbg(afe->dev, "%s(), failed to set clk parent %d\n",
550 static int mt8188_afe_enable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type)
556 regmap_update_bits(afe->regmap, reg, mask, val);
561 static int mt8188_afe_disable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type)
567 regmap_update_bits(afe->regmap, reg, mask, val);
572 int mt8188_afe_enable_reg_rw_clk(struct mtk_base_afe *afe)
574 struct mt8188_afe_private *afe_priv = afe->platform_priv;
577 mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_AUDIO_LOCAL_BUS_SEL]);
580 mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_AUD_INTBUS_SEL]);
583 mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_ADSP_AUDIO_26M]);
586 mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_AFE]);
587 mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS_HP]);
588 mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS]);
593 int mt8188_afe_disable_reg_rw_clk(struct mtk_base_afe *afe)
595 struct mt8188_afe_private *afe_priv = afe->platform_priv;
597 mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS]);
598 mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS_HP]);
599 mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_AFE]);
600 mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_ADSP_AUDIO_26M]);
601 mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_AUD_INTBUS_SEL]);
602 mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_AUDIO_LOCAL_BUS_SEL]);
607 static int mt8188_afe_enable_afe_on(struct mtk_base_afe *afe)
609 regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x1);
613 static int mt8188_afe_disable_afe_on(struct mtk_base_afe *afe)
615 regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x0);
619 static int mt8188_afe_enable_a1sys(struct mtk_base_afe *afe)
621 struct mt8188_afe_private *afe_priv = afe->platform_priv;
624 ret = mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS]);
628 return mt8188_afe_enable_top_cg(afe, MT8188_TOP_CG_A1SYS_TIMING);
631 static int mt8188_afe_disable_a1sys(struct mtk_base_afe *afe)
633 struct mt8188_afe_private *afe_priv = afe->platform_priv;
635 mt8188_afe_disable_top_cg(afe, MT8188_TOP_CG_A1SYS_TIMING);
636 mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS]);
640 static int mt8188_afe_enable_a2sys(struct mtk_base_afe *afe)
642 struct mt8188_afe_private *afe_priv = afe->platform_priv;
645 ret = mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A2SYS]);
649 return mt8188_afe_enable_top_cg(afe, MT8188_TOP_CG_A2SYS_TIMING);
652 static int mt8188_afe_disable_a2sys(struct mtk_base_afe *afe)
654 struct mt8188_afe_private *afe_priv = afe->platform_priv;
656 mt8188_afe_disable_top_cg(afe, MT8188_TOP_CG_A2SYS_TIMING);
657 mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A2SYS]);
661 int mt8188_apll1_enable(struct mtk_base_afe *afe)
663 struct mt8188_afe_private *afe_priv = afe->platform_priv;
666 ret = mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_APLL1_D4]);
670 ret = mt8188_afe_set_clk_parent(afe, afe_priv->clk[MT8188_CLK_TOP_A1SYS_HP_SEL],
675 ret = mt8188_afe_enable_apll_tuner(afe, MT8188_AUD_PLL1);
679 ret = mt8188_afe_enable_a1sys(afe);
686 mt8188_afe_disable_apll_tuner(afe, MT8188_AUD_PLL1);
688 mt8188_afe_set_clk_parent(afe, afe_priv->clk[MT8188_CLK_TOP_A1SYS_HP_SEL],
691 mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_APLL1_D4]);
696 int mt8188_apll1_disable(struct mtk_base_afe *afe)
698 struct mt8188_afe_private *afe_priv = afe->platform_priv;
700 mt8188_afe_disable_a1sys(afe);
701 mt8188_afe_disable_apll_tuner(afe, MT8188_AUD_PLL1);
702 mt8188_afe_set_clk_parent(afe, afe_priv->clk[MT8188_CLK_TOP_A1SYS_HP_SEL],
704 mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_APLL1_D4]);
709 int mt8188_apll2_enable(struct mtk_base_afe *afe)
713 ret = mt8188_afe_enable_apll_tuner(afe, MT8188_AUD_PLL2);
717 ret = mt8188_afe_enable_a2sys(afe);
723 mt8188_afe_disable_apll_tuner(afe, MT8188_AUD_PLL2);
728 int mt8188_apll2_disable(struct mtk_base_afe *afe)
730 mt8188_afe_disable_a2sys(afe);
731 mt8188_afe_disable_apll_tuner(afe, MT8188_AUD_PLL2);
735 int mt8188_afe_enable_main_clock(struct mtk_base_afe *afe)
737 mt8188_afe_enable_top_cg(afe, MT8188_TOP_CG_26M_TIMING);
738 mt8188_afe_enable_afe_on(afe);
742 int mt8188_afe_disable_main_clock(struct mtk_base_afe *afe)
744 mt8188_afe_disable_afe_on(afe);
745 mt8188_afe_disable_top_cg(afe, MT8188_TOP_CG_26M_TIMING);